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3b2e4f542e
When bootstage is used the timer can be inited before the CPU identity is set up, resulting in the checks for the vendor not working. Add a special call to work around this. Signed-off-by: Simon Glass <sjg@chromium.org>
84 lines
1.4 KiB
C
84 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <init.h>
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#include <asm/cpu.h>
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#include <asm/global_data.h>
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#include <asm/processor-flags.h>
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_has_64bit(void)
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{
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return true;
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}
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void enable_caches(void)
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{
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/* Not implemented */
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}
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void disable_caches(void)
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{
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/* Not implemented */
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}
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int dcache_status(void)
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{
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return true;
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}
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int x86_mp_init(void)
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{
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/* Not implemented */
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return 0;
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}
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/* enable SSE features for hardware floating point */
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static void setup_sse_features(void)
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{
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asm ("mov %%cr4, %%rax\n" \
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"or %0, %%rax\n" \
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"mov %%rax, %%cr4\n" \
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: : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax");
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}
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int x86_cpu_reinit_f(void)
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{
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/* set the vendor to Intel so that native_calibrate_tsc() works */
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gd->arch.x86_vendor = X86_VENDOR_INTEL;
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gd->arch.has_mtrr = true;
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if (IS_ENABLED(CONFIG_X86_HARDFP))
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setup_sse_features();
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return 0;
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}
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int cpu_phys_address_size(void)
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{
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return CONFIG_CPU_ADDR_BITS;
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}
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int x86_cpu_init_f(void)
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{
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* this was already done in SPL */
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}
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#endif
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void x86_get_identity_for_timer(void)
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{
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/* set the vendor to Intel so that native_calibrate_tsc() works */
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gd->arch.x86_vendor = X86_VENDOR_INTEL;
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}
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