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dac3ce976a
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
144 lines
4.4 KiB
C
144 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// (C) 2022 Pali Rohár <pali@kernel.org>
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#include <config.h>
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#include <mpc85xx.h>
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#include <asm/mmu.h>
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#include <linux/sizes.h>
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#include <linux/build_bug.h>
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/*
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* NOTE: e500v2 supports only following Book-E page sizes:
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*
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* TLB0:
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* BOOKE_PAGESZ_4K
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*
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* TLB1:
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* BOOKE_PAGESZ_4K
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* BOOKE_PAGESZ_16K
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* BOOKE_PAGESZ_64K
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* BOOKE_PAGESZ_256K
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* BOOKE_PAGESZ_1M
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* BOOKE_PAGESZ_4M
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* BOOKE_PAGESZ_16M
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* BOOKE_PAGESZ_64M
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* BOOKE_PAGESZ_256M
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* BOOKE_PAGESZ_1G
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* BOOKE_PAGESZ_4G
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*/
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 */
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/* ***** - Initial stack in L1 cache 16K */
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 0 * SZ_4K,
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CFG_SYS_INIT_RAM_ADDR_PHYS + 0 * SZ_4K,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 1 * SZ_4K,
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CFG_SYS_INIT_RAM_ADDR_PHYS + 1 * SZ_4K,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 2 * SZ_4K,
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CFG_SYS_INIT_RAM_ADDR_PHYS + 2 * SZ_4K,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 3 * SZ_4K,
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CFG_SYS_INIT_RAM_ADDR_PHYS + 3 * SZ_4K,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Boot page 4K */
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SET_TLB_ENTRY(1, BPTR_VIRT_ADDR,
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0xfffff000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
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0, 0, BOOKE_PAGESZ_4K, 1),
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/* *I*G* - CCSR 1M */
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SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR,
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CFG_SYS_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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/* W**G* - NOR 16M */
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/* This will be changed to *I*G* after relocation to RAM in board_early_init_r() */
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SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE,
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CFG_SYS_FLASH_BASE_PHYS,
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MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
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0, 2, BOOKE_PAGESZ_16M, 1),
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/* *I*G* - CPLD 256K (effective 128K) */
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SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE,
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CFG_SYS_CPLD_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 3, BOOKE_PAGESZ_256K, 1),
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/* *I*G* - NAND 256K */
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SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE,
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CFG_SYS_NAND_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256K, 1),
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/* *I*G* - PCIe MEM (bus 1 and 2) 1G */
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SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT,
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CFG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 5, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCIe MEM (bus 3) 4M (effective 2M) */
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SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT,
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CFG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 6, BOOKE_PAGESZ_4M, 1),
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/* *I*G* - PCIe I/O (all 3 buses) 256K (effective 192K) */
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SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT,
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CFG_SYS_PCIE1_IO_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 7, BOOKE_PAGESZ_256K, 1),
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#ifdef CFG_SYS_INIT_L2_ADDR
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/* ***G* - Initial SRAM in L2 cache 512K */
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SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR,
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CFG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
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0, 8, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + SZ_256K,
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CFG_SYS_INIT_L2_ADDR_PHYS + SZ_256K,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
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0, 9, BOOKE_PAGESZ_256K, 1),
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#endif
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#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
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/* **M** - SDRAM 2G */
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SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE,
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CFG_SYS_DDR_SDRAM_BASE,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
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0, 10, BOOKE_PAGESZ_1G, 1),
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SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + SZ_1G,
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CFG_SYS_DDR_SDRAM_BASE + SZ_1G,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
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0, 11, BOOKE_PAGESZ_1G, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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/*
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* PCIe MEM TLB entry expects that second PCIe MEM window is mapped after the
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* first PCIe MEM window. Check for this requirement.
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*/
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static_assert(CFG_SYS_PCIE1_MEM_VIRT + SZ_512M == CFG_SYS_PCIE2_MEM_VIRT);
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static_assert(CFG_SYS_PCIE1_MEM_PHYS + SZ_512M == CFG_SYS_PCIE2_MEM_PHYS);
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/*
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* PCIe I/O TLB entry expects that all 3 PCIe I/O windows are mapped one after
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* another. Check for this requirement.
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*/
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static_assert(CFG_SYS_PCIE1_IO_VIRT + SZ_64K == CFG_SYS_PCIE2_IO_VIRT);
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static_assert(CFG_SYS_PCIE1_IO_PHYS + SZ_64K == CFG_SYS_PCIE2_IO_PHYS);
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static_assert(CFG_SYS_PCIE2_IO_VIRT + SZ_64K == CFG_SYS_PCIE3_IO_VIRT);
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static_assert(CFG_SYS_PCIE2_IO_PHYS + SZ_64K == CFG_SYS_PCIE3_IO_PHYS);
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