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aec83261b9
Support old DDR3 training code on Turris Omnia, selectable via EEPROM field. Users experiencing DDR3 initialization failures or random crashes of the operating system due to incorrect DDR3 configuration can select the old DDR3 training implementation to fix those issues by setting the EEPROM field "Use old DDR training": eeprom update "Use old DDR training" 1 Signed-off-by: Marek Behún <kabel@kernel.org>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Marek Behún <kabel@kernel.org>
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*/
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#include <asm/arch/soc.h>
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#include <asm/io.h>
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#include "../drivers/ddr/marvell/a38x/old/ddr3_init.h"
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static struct hws_topology_map board_topology_map_1g = {
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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BUS_WIDTH_16, /* memory_width */
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MEM_4G, /* mem_size */
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DDR_FREQ_800, /* frequency */
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0, 0, /* cas_l cas_wl */
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HWS_TEMP_NORMAL, /* temperature */
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HWS_TIM_2T} }, /* timing (force 2t) */
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5, /* Num Of Bus Per Interface*/
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BUS_MASK_32BIT /* Busses mask */
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};
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static struct hws_topology_map board_topology_map_2g = {
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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BUS_WIDTH_16, /* memory_width */
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MEM_8G, /* mem_size */
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DDR_FREQ_800, /* frequency */
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0, 0, /* cas_l cas_wl */
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HWS_TEMP_NORMAL, /* temperature */
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HWS_TIM_2T} }, /* timing (force 2t) */
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5, /* Num Of Bus Per Interface*/
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BUS_MASK_32BIT /* Busses mask */
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};
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/* defined in turris_omnia.c */
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extern int omnia_get_ram_size_gb(void);
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struct hws_topology_map *ddr3_get_topology_map(void)
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{
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if (omnia_get_ram_size_gb() == 2)
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return &board_topology_map_2g;
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else
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return &board_topology_map_1g;
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}
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__weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui)
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{
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return MV_OK;
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}
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