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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
8 lines
247 B
Plaintext
8 lines
247 B
Plaintext
AST2700 using Ibex RISC-V Core as the boot MCU
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M: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
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S: Maintained
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F: arch/riscv/include/asm/arch-ast2700/
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F: board/aspeed/ibex_ast2700/
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F: configs/ibex-ast2700_defconfig
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F: include/configs/ibex_ast2700.h
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