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9057a48af4
This config is causing conflicts with how fdtfile variable is initialized. For K3 devices, CONFIG_DEFAULT_DEVICE_TREE= "ti/k3-<board>.dtb". With CONFIG_TI_FDT_FOLDER_PATH also prefixing "ti", fdtfile is then "ti/ti/k3-<board>.dtb". This variable is updated when fitImage is booted and fails to boot due to the parsing error "ti/ti/". Given that there are no other users of this config other than K3 for now, it is being removed. Since am64x, j721e and j721s2 also define a DEFAULT_FDT_FILE, update them to conform to the DEFAULT_DEVICE_TREE standard. Signed-off-by: Aashvij Shenai <a-shenai@ti.com>
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* https://beagleplay.org/
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*
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* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
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* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
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*/
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#include <efi_loader.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <spl.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct efi_fw_image fw_images[] = {
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{
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.image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID,
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.fw_name = u"BEAGLEPLAY_TIBOOT3",
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.image_index = 1,
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},
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{
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.image_type_id = BEAGLEPLAY_SPL_IMAGE_GUID,
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.fw_name = u"BEAGLEPLAY_SPL",
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.image_index = 2,
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},
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{
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.image_type_id = BEAGLEPLAY_UBOOT_IMAGE_GUID,
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.fw_name = u"BEAGLEPLAY_UBOOT",
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.image_index = 3,
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}
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};
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struct efi_capsule_update_info update_info = {
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.dfu_string = "mmc 0=tiboot3.bin raw 0 2000 mmcpart 1;"
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"tispl.bin fat 0 1;u-boot.img fat 0 1",
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.num_images = ARRAY_SIZE(fw_images),
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.images = fw_images,
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};
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#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
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void set_dfu_alt_info(char *interface, char *devstr)
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{
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if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
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env_set("dfu_alt_info", update_info.dfu_string);
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}
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#endif
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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char fdtfile[50];
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snprintf(fdtfile, sizeof(fdtfile), "%s.dtb", CONFIG_DEFAULT_DEVICE_TREE);
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env_set("fdtfile", fdtfile);
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BOARD_INIT
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/*
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* Enable the 32k Crystal: needed for accurate 32k clock
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* and external clock sources such as wlan 32k input clock
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* supplied from the SoC to the wlan chip.
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*
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* The trim setup can be very highly board type specific choice of the crystal
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* So this is done in the board file, though, in this case, no specific trim
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* is necessary.
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*/
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static void crystal_32k_enable(void)
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{
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/* Only mess with 32k at the start of boot from R5 */
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if (IS_ENABLED(CONFIG_CPU_V7R)) {
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/*
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* We have external 32k crystal, so lets enable it (0x0)
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* and disable bypass (0x0)
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*/
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writel(0x0, MCU_CTRL_LFXOSC_CTRL);
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/* Add any crystal specific TRIM needed here.. */
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/* Make sure to mux the SoC 32k from the crystal */
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writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
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MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
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}
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}
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static void debounce_configure(void)
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{
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/* Configure debounce one time from R5 */
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if (IS_ENABLED(CONFIG_CPU_V7R)) {
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/*
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* Setup debounce time registers.
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* arbitrary values. Times are approx
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*/
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/* 1.9ms debounce @ 32k */
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writel(0x1, CTRLMMR_DBOUNCE_CFG(1));
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/* 5ms debounce @ 32k */
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writel(0x5, CTRLMMR_DBOUNCE_CFG(2));
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/* 20ms debounce @ 32k */
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writel(0x14, CTRLMMR_DBOUNCE_CFG(3));
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/* 46ms debounce @ 32k */
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writel(0x18, CTRLMMR_DBOUNCE_CFG(4));
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/* 100ms debounce @ 32k */
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writel(0x1c, CTRLMMR_DBOUNCE_CFG(5));
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/* 156ms debounce @ 32k */
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writel(0x1f, CTRLMMR_DBOUNCE_CFG(6));
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}
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}
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void spl_board_init(void)
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{
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crystal_32k_enable();
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debounce_configure();
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}
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#endif
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