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f874dec10a
Initialize register in cv1800b ethernet phy to make it compatible with generic phy driver Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
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*/
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/mii.h>
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#define REG_EPHY_TOP_WRAP (u32 *)0x03009800
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#define REG_EPHY_BASE (u32 *)0x03009000
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#define REG_EPHY_CTL REG_EPHY_TOP_WRAP
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#define REG_EPHY_APB_RW_SEL REG_EPHY_TOP_WRAP + 1
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/* Page 0 register */
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#define REG_PHY_ID1 REG_EPHY_BASE + MII_PHYSID1
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#define REG_PHY_ID2 REG_EPHY_BASE + MII_PHYSID2
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#define REG_PHY_PAGE_SEL REG_EPHY_BASE + 0x1f
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/* Page 5 register */
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#define REG_PD_EN_CTL REG_EPHY_BASE + 0x10
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/* REG_EPHY_CTL */
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#define REG_EPHY_SHUTDOWN BIT(0)
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#define REG_EPHY_ANA_RST_N BIT(1)
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#define REG_EPHY_DIG_RST_N BIT(2)
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#define REG_EPHY_MAIN_RST_N BIT(3)
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/* REG_PD_EN_CTL */
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#define REG_EN_ETH_TXRT BIT(0)
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#define REG_EN_ETH_CLK100M BIT(1)
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#define REG_EN_ETH_CLK125M BIT(2)
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#define REG_EN_ETH_PLL_LCKDET BIT(3)
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#define REG_EN_ETH_RXADC BIT(4)
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#define REG_EN_ETH_RXPGA BIT(5)
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#define REG_EN_ETH_RXRT BIT(6)
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#define REG_EN_ETH_TXCROSSOVER BIT(7)
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#define REG_PD_ETH_PLL BIT(8)
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#define REG_PD_ETH_TXDAC BIT(9)
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#define REG_PD_ETH_TXDACBST BIT(10)
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#define REG_PD_ETH_TXECHO BIT(11)
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#define REG_PD_ETH_TXDRV_NMOS BIT(12)
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#define REG_PD_ETH_TXLDO BIT(13)
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void cv1800b_ephy_init(void)
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{
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u32 reg;
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u32 phy_id = 1;
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/* enable direct memory access for phy register */
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writel(1, REG_EPHY_APB_RW_SEL);
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reg = readl(REG_EPHY_CTL);
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reg &= ~REG_EPHY_SHUTDOWN;
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reg |= REG_EPHY_ANA_RST_N | REG_EPHY_DIG_RST_N | REG_EPHY_MAIN_RST_N;
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writel(reg, REG_EPHY_CTL);
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/* switch to page 5 */
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writel(5 << 8, REG_PHY_PAGE_SEL);
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reg = readl(REG_PD_EN_CTL);
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reg &= ~(REG_PD_ETH_TXLDO | REG_PD_ETH_TXDRV_NMOS | REG_PD_ETH_TXDAC | REG_PD_ETH_PLL);
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reg |= REG_EN_ETH_TXRT | REG_EN_ETH_CLK100M | REG_EN_ETH_CLK125M
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| REG_EN_ETH_PLL_LCKDET | REG_EN_ETH_RXADC | REG_EN_ETH_RXPGA | REG_EN_ETH_RXRT;
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writel(reg, REG_PD_EN_CTL);
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/* switch to page 0 */
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writel(0 << 8, REG_PHY_PAGE_SEL);
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/*
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* As the phy_id in the cv1800b PHY register is initialized to 0, it
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* is necessary to manually initialize the phy_id to an arbitrary
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* value so that it could corresponds to the generic PHY driver.
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*/
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writel(phy_id >> 16, REG_PHY_ID1);
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writel(phy_id & 0xffff, REG_PHY_ID2);
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/* switch to MDIO control */
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writel(0, REG_EPHY_APB_RW_SEL);
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}
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