mirror of
https://github.com/smaeul/u-boot.git
synced 2025-09-15 14:36:03 +01:00
642ee26bc8
JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and is targeting Autonomous Mobile Robots (AMR). It features: * LPDDR4X (up to 16GB) * 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131) * PCIe 3.0 4-lane on M.2 M-key connector * PCIe 2.1 1-lane on M.2 E-key * USB 2.0 on M.2 E-key * 2x USB3 OTG type-c ports with DP Alt-Mode * USB2 host port * HDMI output * 2x camera connectors, each exposing: * 2-lane MIPI-CSI * 1v2, 1v8, 2v8 power rails * I2C bus * GPIOs * PPS input * CAN * RS485 UART * FAN connector * SD card slot * eMMC (up to 256GB) * RTC backup battery * Companion microcontroller * ISL1208 RTC emulation * AMC6821 PWM emulation * On/off buzzer control * Secure Element * 80-pin Mezzanine connector for daughterboards: * GPIOs * 1Gbps Ethernet * PCIe 2.1 1-lane * 2x 2-lane MIPI-CSI * ADC channel * I2C bus * PWM * UART * SPI * SDIO * CAN * I2S * 1v8, 3v3, 5v0, dc-in (12-24V) power rails The Device Tree comes from next-20240110 Linux kernel. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
|
|
*/
|
|
|
|
#include <phy.h>
|
|
#include <eth_phy.h>
|
|
|
|
#include <asm/types.h>
|
|
#include <asm/arch-rockchip/cru_rk3588.h>
|
|
#include <asm/arch-rockchip/hardware.h>
|
|
#include <asm/arch-rockchip/ioc_rk3588.h>
|
|
#include <asm-generic/u-boot.h>
|
|
#include <dm/device.h>
|
|
#include <dm/uclass-id.h>
|
|
#include <linux/bitfield.h>
|
|
|
|
#include "../common/common.h"
|
|
|
|
#define GPIO2C3_SEL_MASK GENMASK(15, 12)
|
|
#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
|
|
|
|
#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
|
|
#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
|
|
#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
|
|
#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
|
|
|
|
#define REFCLKO25M_ETH0_OUT_EN BIT(4)
|
|
|
|
void setup_eth0refclko(void)
|
|
{
|
|
/* Configure and enable ETH0_REFCLKO_25MHz */
|
|
static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
|
|
static struct rk3588_cru * const cru = (void *)CRU_BASE;
|
|
|
|
/* 1. Pinmux */
|
|
rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
|
|
/* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
|
|
rk_clrsetreg(&cru->clksel_con[15],
|
|
REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
|
|
REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
|
|
/* 3. Enable clock */
|
|
rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
|
|
}
|
|
|
|
int rockchip_early_misc_init_r(void)
|
|
{
|
|
setup_boottargets();
|
|
|
|
setup_eth0refclko();
|
|
|
|
return 0;
|
|
}
|