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f0d356610b
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector * Gigabit Ethernet with on-module GbE PHY * HDMI/eDP * MIPI-DSI * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) * HDMI input over FPC connector * CAN * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host * PCIe - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes * on-module ATtiny816 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment The support is added for Tiger on Haikou devkit, similarly to RK3399 Puma and PX30 Ringneck. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
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*/
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#include <phy.h>
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#include <eth_phy.h>
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#include <asm/types.h>
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#include <asm/arch-rockchip/cru_rk3588.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/ioc_rk3588.h>
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#include <asm-generic/u-boot.h>
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#include <dm/device.h>
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#include <dm/uclass-id.h>
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#include <linux/bitfield.h>
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#include "../common/common.h"
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#define GPIO2C3_SEL_MASK GENMASK(15, 12)
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#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
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#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
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#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
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#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
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#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
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#define REFCLKO25M_ETH0_OUT_EN BIT(4)
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void setup_eth0refclko(void)
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{
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/* Configure and enable ETH0_REFCLKO_25MHz */
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static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
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static struct rk3588_cru * const cru = (void *)CRU_BASE;
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/* 1. Pinmux */
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rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
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/* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
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rk_clrsetreg(&cru->clksel_con[15],
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REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
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REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
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/* 3. Enable clock */
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rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
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}
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int rockchip_early_misc_init_r(void)
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{
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setup_boottargets();
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setup_eth0refclko();
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return 0;
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}
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