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https://github.com/smaeul/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
94 lines
2.0 KiB
C
94 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Author: Greg Malysa <greg.malysa@timesys.com>
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*
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* Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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*/
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#include <clk.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <linux/compiler_types.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include "clk.h"
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#define ADI_CLK_PLL_GENERIC "adi_clk_pll_generic"
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struct clk_sc5xx_cgu_pll {
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struct clk clk;
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void __iomem *base;
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u32 mask;
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u32 max;
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u32 m_offset;
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u8 shift;
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bool half_m;
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};
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#define to_clk_sc5xx_cgu_pll(_clk) container_of(_clk, struct clk_sc5xx_cgu_pll, clk)
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static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk)
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{
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struct clk_sc5xx_cgu_pll *pll = to_clk_sc5xx_cgu_pll(dev_get_clk_ptr(clk->dev));
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 reg = readl(pll->base);
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u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset;
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if (m == 0)
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m = pll->max;
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if (pll->half_m)
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return parent_rate * m * 2;
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return parent_rate * m;
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}
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static const struct clk_ops clk_sc5xx_cgu_pll_ops = {
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.get_rate = sc5xx_cgu_pll_get_rate,
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};
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struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,
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void __iomem *base, u8 shift, u8 width, u32 m_offset,
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bool half_m)
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{
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struct clk_sc5xx_cgu_pll *pll;
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struct clk *clk;
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int ret;
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char *drv_name = ADI_CLK_PLL_GENERIC;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->base = base;
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pll->shift = shift;
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pll->mask = GENMASK(width - 1, 0) << shift;
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pll->max = pll->mask + 1;
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pll->m_offset = m_offset;
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pll->half_m = half_m;
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clk = &pll->clk;
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ret = clk_register(clk, drv_name, name, parent_name);
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if (ret) {
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pr_err("Failed to register %s in %s: %d\n", name, __func__, ret);
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_adi_pll_generic) = {
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.name = ADI_CLK_PLL_GENERIC,
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.id = UCLASS_CLK,
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.ops = &clk_sc5xx_cgu_pll_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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