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767a1e57fa
Add the missing PCIe clk_req function for the x1e80100 TLMM. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-pinctrl-v1-3-4df323d90397@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm x1e80100 pinctrl
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*
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* (C) Copyright 2024 Linaro Ltd.
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*
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*/
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#include <dm.h>
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#include "pinctrl-qcom.h"
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#define MAX_PIN_NAME_LEN 32
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static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
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static const struct pinctrl_function msm_pinctrl_functions[] = {
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{"qup2_se5", 1},
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{"pcie3_clk", 1},
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{"pcie4_clk", 1},
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{"pcie5_clk", 1},
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{"pcie6a_clk", 1},
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{"pcie6b_clk", 1},
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{"gpio", 0},
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};
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#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
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{ \
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.name = pg_name, \
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.ctl_reg = ctl, \
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.io_reg = 0, \
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.pull_bit = pull, \
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.drv_bit = drv, \
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.oe_bit = -1, \
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.in_bit = -1, \
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.out_bit = -1, \
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}
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#define UFS_RESET(pg_name, ctl) \
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{ \
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.name = pg_name, \
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.ctl_reg = ctl, \
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.io_reg = ctl + 0x4, \
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.pull_bit = 3, \
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.drv_bit = 0, \
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.oe_bit = -1, \
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.in_bit = -1, \
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.out_bit = 0, \
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}
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static const struct msm_special_pin_data msm_special_pins_data[] = {
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[0] = UFS_RESET("ufs_reset", 0xf9000),
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[1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xf2000, 14, 6),
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[2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xf2000, 11, 3),
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[3] = SDC_QDSD_PINGROUP("sdc2_data", 0xf2000, 9, 0),
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};
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static const char *x1e80100_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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return msm_pinctrl_functions[selector].name;
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}
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static const char *x1e80100_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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if (selector >= 238 && selector <= 241)
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snprintf(pin_name, MAX_PIN_NAME_LEN,
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msm_special_pins_data[selector - 238].name);
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else
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snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
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return pin_name;
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}
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static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
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unsigned int selector)
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{
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return msm_pinctrl_functions[selector].val;
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}
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static struct msm_pinctrl_data x1e80100_data = {
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.pin_data = {
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.pin_count = 242,
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.special_pins_start = 238,
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.special_pins_data = msm_special_pins_data,
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},
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.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
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.get_function_name = x1e80100_get_function_name,
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.get_function_mux = x1e80100_get_function_mux,
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.get_pin_name = x1e80100_get_pin_name,
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};
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static const struct udevice_id msm_pinctrl_ids[] = {
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{ .compatible = "qcom,x1e80100-tlmm", .data = (ulong)&x1e80100_data },
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{ /* Sentinel */ }
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};
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U_BOOT_DRIVER(pinctrl_x1e80100) = {
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.name = "pinctrl_x1e80100",
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.id = UCLASS_NOP,
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.of_match = msm_pinctrl_ids,
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.ops = &msm_pinctrl_ops,
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.bind = msm_pinctrl_bind,
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};
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