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https://github.com/smaeul/u-boot.git
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35d967f5a8
In the older USB controllers like for example in ChipIdea controller used by the Tegra 2 the "USBADRA: Device Address Advance" bitflag does not exist, so the new device address set during SET_ADDRESS can't be deferred by hardware, which causes the host to not recognize the device and give an error. Instead store it until ep completes to apply the change into the hw register as Linux kernel does. This should fix regression on old and and be compatible with newer controllers. Inspired by: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ef15e5490edc7edf808d3477ab32e0e320792f65 Signed-off-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20241126072956.64778-2-clamor95@gmail.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
155 lines
3.3 KiB
C
155 lines
3.3 KiB
C
/*
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* Copyright 2011, Marvell Semiconductor Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __GADGET__CI_UDC_H__
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#define __GADGET__CI_UDC_H__
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#define NUM_ENDPOINTS 6
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#ifdef CONFIG_CI_UDC_HAS_HOSTPC
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struct ci_udc {
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u32 usbcmd; /* 0x130 */
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u32 usbsts; /* 0x134 */
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u32 pad1[3];
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u32 devaddr; /* 0x144 */
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u32 epinitaddr; /* 0x148 */
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u32 pad2[10];
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u32 portsc; /* 0x174 */
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u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
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u32 hostpc1_devlc; /* 0x1b4 */
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u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
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u32 usbmode; /* 0x1f8 */
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u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
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u32 epsetupstat; /* 0x208 */
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u32 epprime; /* 0x20c */
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u32 epflush; /* 0x210 */
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u32 epstat; /* 0x214 */
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u32 epcomp; /* 0x218 */
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u32 epctrl[16]; /* 0x21c */
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};
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#else
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struct ci_udc {
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u32 usbcmd; /* 0x140 */
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u32 usbsts; /* 0x144 */
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u32 pad1[3];
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u32 devaddr; /* 0x154 */
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u32 epinitaddr; /* 0x158 */
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u32 pad2[10];
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u32 portsc; /* 0x184 */
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u32 pad3[8];
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u32 usbmode; /* 0x1a8 */
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u32 epstat; /* 0x1ac */
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u32 epprime; /* 0x1b0 */
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u32 epflush; /* 0x1b4 */
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u32 pad4;
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u32 epcomp; /* 0x1bc */
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u32 epctrl[16]; /* 0x1c0 */
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};
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#define PTS_ENABLE 2
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#define PTS(x) (((x) & 0x3) << 30)
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#define PFSC (1 << 24)
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#endif
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#define MICRO_8FRAME 0x8
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#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
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#define USBCMD_FS2 (1 << 15)
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#define USBCMD_RST (1 << 1)
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#define USBCMD_RUN (1)
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#define STS_SLI (1 << 8)
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#define STS_URI (1 << 6)
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#define STS_PCI (1 << 2)
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#define STS_UEI (1 << 1)
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#define STS_UI (1 << 0)
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#define USBMODE_DEVICE 2
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#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
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#define EPT_RX(x) (1 << ((x) & 0xffff))
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#define CTRL_TXE (1 << 23)
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#define CTRL_TXR (1 << 22)
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#define CTRL_RXE (1 << 7)
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#define CTRL_RXR (1 << 6)
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#define CTRL_TXT_BULK (2 << 18)
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#define CTRL_RXT_BULK (2 << 2)
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struct ci_req {
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struct usb_request req;
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struct list_head queue;
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/* Bounce buffer allocated if needed to align the transfer */
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uint8_t *b_buf;
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uint32_t b_len;
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/* Buffer for the current transfer. Either req.buf/len or b_buf/len */
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uint8_t *hw_buf;
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uint32_t hw_len;
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uint32_t dtd_count;
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};
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struct ci_ep {
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struct usb_ep ep;
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struct list_head queue;
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bool req_primed;
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const struct usb_endpoint_descriptor *desc;
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};
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struct ci_drv {
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struct usb_gadget gadget;
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struct ci_req *ep0_req;
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bool ep0_data_phase;
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struct usb_gadget_driver *driver;
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struct ehci_ctrl *ctrl;
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struct ept_queue_head *epts;
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uint8_t *items_mem;
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struct ci_ep ep[NUM_ENDPOINTS];
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u8 next_device_address;
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};
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struct ept_queue_head {
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unsigned config;
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unsigned current; /* read-only */
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unsigned next;
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unsigned info;
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unsigned page0;
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unsigned page1;
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unsigned page2;
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unsigned page3;
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unsigned page4;
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unsigned reserved_0;
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unsigned char setup_data[8];
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unsigned reserved_1;
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unsigned reserved_2;
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unsigned reserved_3;
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unsigned reserved_4;
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};
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#define CFG_MAX_PKT(n) ((n) << 16)
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#define CFG_ZLT (1 << 29) /* stop on zero-len xfer */
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#define CFG_IOS (1 << 15) /* IRQ on setup */
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struct ept_queue_item {
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unsigned next;
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unsigned info;
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unsigned page0;
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unsigned page1;
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unsigned page2;
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unsigned page3;
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unsigned page4;
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unsigned reserved;
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};
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#define TERMINATE 1
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#define INFO_BYTES(n) ((n) << 16)
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#define INFO_IOC (1 << 15)
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#define INFO_ACTIVE (1 << 7)
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#define INFO_HALTED (1 << 6)
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#define INFO_BUFFER_ERROR (1 << 5)
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#define INFO_TX_ERROR (1 << 3)
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#endif
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