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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Based on what "git diff" suggests, rename a device tree for imx8mm_venice_defconfig and imx8mp_venice_defconfig Signed-off-by: Tom Rini <trini@konsulko.com> --- Cc: Tim Harvey <tharvey@gateworks.com>
77 lines
1.8 KiB
YAML
77 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek System Clock Controller for MT8195
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The clock architecture in Mediatek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys provides most of PLLs which generated from SoC 26m.
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The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8195-topckgen
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- mediatek,mt8195-infracfg_ao
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- mediatek,mt8195-apmixedsys
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- mediatek,mt8195-pericfg_ao
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8195-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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infracfg_ao: syscon@10001000 {
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compatible = "mediatek,mt8195-infracfg_ao", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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apmixedsys: syscon@1000c000 {
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compatible = "mediatek,mt8195-apmixedsys", "syscon";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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pericfg_ao: syscon@11003000 {
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compatible = "mediatek,mt8195-pericfg_ao", "syscon";
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reg = <0x11003000 0x1000>;
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#clock-cells = <1>;
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};
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