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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Based on what "git diff" suggests, rename a device tree for imx8mm_venice_defconfig and imx8mp_venice_defconfig Signed-off-by: Tom Rini <trini@konsulko.com> --- Cc: Tim Harvey <tharvey@gateworks.com>
93 lines
2.1 KiB
YAML
93 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel SDHCI controller
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maintainers:
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- Aubin Constans <aubin.constans@microchip.com>
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- Nicolas Ferre <nicolas.ferre@microchip.com>
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description:
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Bindings for the SDHCI controller found in Atmel/Microchip SoCs.
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properties:
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compatible:
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oneOf:
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- enum:
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- atmel,sama5d2-sdhci
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- microchip,sam9x60-sdhci
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- items:
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- enum:
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- microchip,sam9x7-sdhci
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- microchip,sama7g5-sdhci
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- const: microchip,sam9x60-sdhci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: hclock
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- description: multclk
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- description: baseclk
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minItems: 2
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clock-names:
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items:
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- const: hclock
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- const: multclk
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- const: baseclk
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minItems: 2
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microchip,sdcal-inverted:
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type: boolean
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description:
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When present, polarity on the SDCAL SoC pin is inverted. The default
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polarity for this signal is described in the datasheet. For instance on
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SAMA5D2, the pin is usually tied to the GND with a resistor and a
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capacitor (see "SDMMC I/O Calibration" chapter).
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- $ref: sdhci-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- atmel,sama5d2-sdhci
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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mmc@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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assigned-clocks = <&sdmmc0_gclk>;
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assigned-clock-rates = <480000000>;
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};
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