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9efcb10a09
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
13 lines
234 B
C
13 lines
234 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#endif /* __CONFIG_H */
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