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f38956a687
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
336 lines
11 KiB
C
336 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* (C) 2022 Pali Rohár <pali@kernel.org> */
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#ifndef _CONFIG_TURRIS_1X_H
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#define _CONFIG_TURRIS_1X_H
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#include <linux/sizes.h>
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/*
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* Turris 1.x memory map:
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*
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* 0x0000_0000 - 0x7fff_ffff 2 GB DDR cacheable
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* 0x8000_0000 - 0xbfff_ffff 1 GB PCIe MEM (bus 1-2) non-cacheable
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* 0xc000_0000 - 0xc01f_ffff 2 MB PCIe MEM (bus 3) non-cacheable
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* 0xc020_0000 - 0xeeff_ffff 750 MB unused
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* 0xef00_0000 - 0xefff_ffff 16 MB NOR (CS0) non-cacheable
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* 0xf000_0000 - 0xf8f7_ffff 143 MB unused
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* 0xf8f8_0000 - 0xf8ff_ffff 512 kB L2 SRAM cacheable (early boot, SD card only)
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* 0xf900_0000 - 0xff6f_ffff 103 MB unused
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* 0xff70_0000 - 0xff7f_ffff 1 MB CCSR non-cacheable (SPL only)
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* 0xff80_0000 - 0xff83_ffff 256 kB NAND (CS1) non-cacheable
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* 0xffa0_0000 - 0xffa1_ffff 128 kB CPLD (CS3) non-cacheable
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* 0xffc0_0000 - 0xffc2_ffff 192 kB PCIe IO non-cacheable
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* 0xffd0_0000 - 0xffd0_3fff 16 kB L1 stack cacheable (early boot)
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* 0xffe0_0000 - 0xffef_ffff 1 MB CCSR non-cacheable (not in SPL)
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* 0xffff_f000 - 0xffff_ffff 4 kB Boot page non-cacheable
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*/
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/*
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* Global settings
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*/
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/*
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* CONFIG_ENABLE_36BIT_PHYS needs to be always defined when processor supports
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* 36-bit addressing (which is case for P2020), also when only 32-bit addressing
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* mode is used. Name of this config option is misleading and should have been
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* called SUPPORT instead of ENABLE.
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* When CONFIG_PHYS_64BIT is set then 36-bit addressing is used, when unset then
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* 32-bit addressing is used. Name of this config option is misleading too and
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* should have been called 36BIT and ENABLED, not 64BIT.
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* Due to performance reasons (see document AN4064), Turris 1.x boards use only
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* 32-bit addressing. Also all config options are currently defined only for
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* 32-bit addressing, so compiling U-Boot for 36-bit addressing is not possible
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* yet.
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*/
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#ifdef CONFIG_PHYS_64BIT
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#error "36-bit addressing is not implemented for this board"
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#endif
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/*
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* Boot settings
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*/
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/*
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* Booting from SD card
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* BootROM configures L2 cache as SRAM, loads image from SD card into L2 SRAM
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* and starts executing directly _start entry point in L2 SRAM. Therefore reset
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* vector is not used and maximal size of the image is L2 cache size. For builds
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* with SPL there is no limit of U-Boot proper as BootROM loads SPL which then
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* loads U-Boot proper directly into DDR.
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*/
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/*
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* For SD card builds without SPL it is needed to set CONFIG_SYS_RAMBOOT
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*
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* if CONFIG_XPL_BUILD
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* if CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
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* define CONFIG_SPL_MAX_SIZE = (CONFIG_SYS_L2_SIZE+CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
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* * SZ_512)
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* else
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* define CONFIG_SPL_MAX_SIZE = CONFIG_SYS_L2_SIZE
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*/
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#ifdef CONFIG_SDCARD
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#define CFG_SYS_MMC_U_BOOT_SIZE CONFIG_BOARD_SIZE_LIMIT
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#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
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#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
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#endif
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/*
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* Booting from NOR
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* Last 4kB page of the NOR is mapped into CPU address space and CPU starts
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* executing last instruction of that page, which is reset vector address.
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* We have 16 MB large NOR memory, so define correct reset vector address.
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*
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* CONFIG_RESET_VECTOR_ADDRESS = (CONFIG_SYS_FLASH_BASE + SZ_16M - 4)
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*/
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/*
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* CONFIG_BOARD_SIZE_LIMIT must be hex number because it is used in Makefile.
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* For NOR build, size of the U-Boot binary must always be 768 kB.
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* For SD card build with SPL, there is no limit, just broken build system which
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* cannot fill CFG_SYS_MMC_U_BOOT_SIZE and CONFIG_SYS_MONITOR_LEN values
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* automatically. So choose it as lowest value as possible with which build
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* process does not fail, to minimize final binary size.
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* For SD card build without SPL, there is upper limit of L2 cache size.
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*
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* if SDCARD
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* CONFIG_BOARD_SIZE_LIMIT = 0x000c0000 // 768 kB
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* elif SPL
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* CONFIG_BOARD_SIZE_LIMIT = 0x00100000 // 1 MB
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* else
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* CONFIG_BOARD_SIZE_LIMIT = 0x00080000 // 512 kB - must be same as CONFIG_SYS_L2_SIZE
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*/
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/*
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* Initial stack in L1 cache
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*/
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#define CFG_SYS_INIT_RAM_ADDR 0xffd00000
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#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
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#define CFG_SYS_INIT_RAM_SIZE SZ_16K
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#define CFG_SYS_GBL_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CFG_SYS_INIT_SP_OFFSET CFG_SYS_GBL_DATA_OFFSET
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/*
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* Initial SRAM in L2 cache
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*/
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/* Initial SRAM is used only for SD card boot in first stage image */
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#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
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#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
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/*
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* CONFIG_SPL_RELOC_TEXT_BASE = CONFIG_SYS_MONITOR_BASE
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* CONFIG_SPL_GD_ADDR = (CFG_SYS_INIT_L2_ADDR + 112 * SZ_1K)
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* CONFIG_SPL_RELOC_STACK = (CFG_SYS_INIT_L2_ADDR + 116 * SZ_1K)
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* CONFIG_SPL_RELOC_MALLOC_ADDR = (CFG_SYS_INIT_L2_ADDR + 148 * SZ_1K)
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* CONFIG_SPL_RELOC_MALLOC_SIZE = (364 * SZ_1K)
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*/
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#endif
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/*
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* CCSR
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*/
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#define CFG_SYS_CCSRBAR 0xffe00000
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#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
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/*
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* CFG_SYS_CCSRBAR_PHYS_HIGH = 0x0
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*/
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/*
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* U-Boot _start code expects that if CCSRBAR is configured to its default
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* location and automatically relocate it to the new CONFIG_SYS_CCSRBAR_PHYS
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* location. Relocation to the new location can be skipped by defining macro
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* CONFIG_SYS_CCSR_DO_NOT_RELOCATE.
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*
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* All addresses in device tree are set to according the new relocated CCSRBAR.
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* So device tree code cannot be used when CONFIG_SYS_CCSR_DO_NOT_RELOCATE is
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* set.
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*
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* If CCSRBAR is not configured to its default location then _start code hangs
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* or crashes.
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*
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* So relocation of CCSRBAR must be disabled in every code which runs before
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* U-Boot proper (e.g. SPL), otherwise U-Boot proper's _start code crashes.
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*/
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/*
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* DDR
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*/
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#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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#define CFG_SYS_I2C_PCA9557_ADDR 0x18
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#define SPD_EEPROM_ADDRESS 0x52
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/*
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* NOR
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*/
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#define CFG_SYS_FLASH_BASE 0xef000000
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#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
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#define CFG_RESET_VECTOR_ADDRESS (CFG_SYS_FLASH_BASE + SZ_16M - 4)
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/*
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* CONFIG_SYS_BR0_PRELIM = (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V)
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* CONFIG_SYS_OR0_PRELIM = (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS
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* | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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*/
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/*
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* NAND
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*/
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#define CFG_SYS_NAND_BASE 0xff800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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/*
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* CONFIG_SYS_BR1_PRELIM = BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V)
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* CONFIG_SYS_OR1_PRELIM = (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT
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* | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
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*/
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
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/*
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* CPLD
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*/
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#define CFG_SYS_CPLD_BASE 0xffa00000
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#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
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/*
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* CONFIG_SYS_BR3_PRELIM = (BR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V)
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* CONFIG_SYS_OR3_PRELIM = (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15
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* | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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*/
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/*
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* Serial Port
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*/
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#if !CONFIG_IS_ENABLED(DM_SERIAL)
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#define CFG_SYS_NS16550_CLK get_bus_freq(0)
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#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x4500)
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#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR + 0x4600)
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#endif
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/*
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* PCIe
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*/
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/* PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card */
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#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
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#define CFG_SYS_PCIE1_MEM_PHYS CFG_SYS_PCIE1_MEM_VIRT
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#define CFG_SYS_PCIE1_IO_PHYS CFG_SYS_PCIE1_IO_VIRT
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/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
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#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CFG_SYS_PCIE2_MEM_PHYS CFG_SYS_PCIE2_MEM_VIRT
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#define CFG_SYS_PCIE2_IO_PHYS CFG_SYS_PCIE2_IO_VIRT
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/* PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller */
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#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
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#define CFG_SYS_PCIE3_IO_VIRT 0xffc20000
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#define CFG_SYS_PCIE3_MEM_PHYS CFG_SYS_PCIE3_MEM_VIRT
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#define CFG_SYS_PCIE3_IO_PHYS CFG_SYS_PCIE3_IO_VIRT
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/*
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* eSDHC
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*/
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#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
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#define SDHC_WP_IS_GPIO /* SDHC_WP pin is not connected to SD card slot, it is GPIO pin */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_SYS_BOOTMAPSZ SZ_64M /* Initial Memory for Linux */
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/*
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* Environment Configuration
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*/
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#ifdef CONFIG_SDCARD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(NVME, nvme, 0) \
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func(SCSI, scsi, 0) \
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func(USB, usb, 0) \
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func(USB, usb, 1) \
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func(USB, usb, 2) \
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func(USB, usb, 3) \
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func(USB, usb, 4) \
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func(UBIFS, ubifs, 0, rootfs, rootfs, 512) \
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func(UBIFS, ubifs, 1, rootfs, rootfs, 2048) \
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func(DHCP, dhcp, na)
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#else
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(NVME, nvme, 0) \
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func(SCSI, scsi, 0) \
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func(USB, usb, 0) \
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func(USB, usb, 1) \
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func(USB, usb, 2) \
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func(USB, usb, 3) \
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func(USB, usb, 4) \
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func(DHCP, dhcp, na)
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#endif
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#include <config_distro_bootcmd.h>
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/* These boot source switches macros must be constant numbers as they are stringified */
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xc8
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#define __SW_BOOT_SPI 0x28
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#define __SW_BOOT_SD 0x68
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#define __SW_BOOT_SD2 0x18
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#define __SW_BOOT_NAND 0xe8
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#define __SW_BOOT_PCIE 0xa8
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#define __SW_NOR_BANK_MASK 0xfd
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#define __SW_NOR_BANK_UP 0x00
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#define __SW_NOR_BANK_LO 0x02
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#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
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#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
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#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
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#include "p1_p2_bootsrc.h"
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#define REBOOT_ENV_SETTINGS \
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RST_NOR_UP_CMD(reboot_to_nor, echo Rebooting to NOR bootloader;) \
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RST_SD_CMD(reboot_to_sd, echo Rebooting to SD bootloader;) \
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RST_DEF_CMD(reboot_to_def, echo Rebooting to default bootloader;) \
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""
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#define BOOTCMD_RESCUE \
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"setenv bootargs root=mtd2 ro rootfstype=jffs2 console=ttyS0,115200; " \
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"mw.b 0xffa00002 0x03; " \
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"bootm 0xef020000 - 0xef000000" \
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""
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#define CFG_EXTRA_ENV_SETTINGS \
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"fdt_addr_r=0x2000000\0" \
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"kernel_addr_r=0x2100000\0" \
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"scriptaddr=0x3000000\0" \
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"pxefile_addr_r=0x3100000\0" \
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"ramdisk_addr_r=0x4000000\0" \
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"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
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"fdt_addr=0xef000000\0" \
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"bootcmd_rescue=" BOOTCMD_RESCUE "\0" \
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REBOOT_ENV_SETTINGS \
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BOOTENV
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#endif /* _CONFIG_TURRIS_1X_H */
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