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ece4e5804f
This patch adds clock driver support for MediaTek MT7987 SoC Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
207 lines
6.1 KiB
C
207 lines
6.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 MediaTek Inc.
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* Author: Lu Tang <Lu.Tang@mediatek.com>
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT7987_H
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#define _DT_BINDINGS_CLK_MT7987_H
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/* INFRACFG */
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#define CLK_INFRA_MUX_UART0_SEL 0
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#define CLK_INFRA_MUX_UART1_SEL 1
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#define CLK_INFRA_MUX_UART2_SEL 2
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#define CLK_INFRA_MUX_SPI0_SEL 3
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#define CLK_INFRA_MUX_SPI1_SEL 4
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#define CLK_INFRA_MUX_SPI2_BCK_SEL 5
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#define CLK_INFRA_PWM_BCK_SEL 6
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8
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#define CLK_INFRA_66M_GPT_BCK 9
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#define CLK_INFRA_66M_PWM_HCK 10
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#define CLK_INFRA_66M_PWM_BCK 11
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#define CLK_INFRA_133M_CQDMA_BCK 12
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#define CLK_INFRA_66M_AUD_SLV_BCK 13
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#define CLK_INFRA_AUD_26M 14
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#define CLK_INFRA_AUD_L 15
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#define CLK_INFRA_AUD_AUD 16
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#define CLK_INFRA_AUD_EG2 17
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#define CLK_INFRA_DRAMC_F26M 18
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#define CLK_INFRA_133M_DBG_ACKM 19
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#define CLK_INFRA_66M_AP_DMA_BCK 20
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#define CLK_INFRA_MSDC200_SRC 21
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#define CLK_INFRA_66M_SEJ_BCK 22
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#define CLK_INFRA_PRE_CK_SEJ_F13M 23
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#define CLK_INFRA_66M_TRNG 24
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#define CLK_INFRA_26M_THERM_SYSTEM 25
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#define CLK_INFRA_I2C_BCK 26
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#define CLK_INFRA_66M_UART0_PCK 27
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#define CLK_INFRA_66M_UART1_PCK 28
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#define CLK_INFRA_66M_UART2_PCK 29
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#define CLK_INFRA_52M_UART0_CK 30
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#define CLK_INFRA_52M_UART1_CK 31
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#define CLK_INFRA_52M_UART2_CK 32
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#define CLK_INFRA_NFI 33
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#define CLK_INFRA_66M_NFI_HCK 34
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#define CLK_INFRA_104M_SPI0 35
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#define CLK_INFRA_104M_SPI1 36
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#define CLK_INFRA_104M_SPI2_BCK 37
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#define CLK_INFRA_66M_SPI0_HCK 38
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#define CLK_INFRA_66M_SPI1_HCK 39
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#define CLK_INFRA_66M_SPI2_HCK 40
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#define CLK_INFRA_66M_FLASHIF_AXI 41
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#define CLK_INFRA_RTC 42
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#define CLK_INFRA_26M_ADC_BCK 43
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#define CLK_INFRA_RC_ADC 44
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#define CLK_INFRA_MSDC400 45
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#define CLK_INFRA_MSDC2_HCK 46
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#define CLK_INFRA_133M_MSDC_0_HCK 47
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#define CLK_INFRA_66M_MSDC_0_HCK 48
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#define CLK_INFRA_133M_CPUM_BCK 49
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#define CLK_INFRA_BIST2FPC 50
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#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51
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#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52
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#define CLK_INFRA_133M_USB_HCK 53
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#define CLK_INFRA_133M_USB_HCK_CK_P1 54
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#define CLK_INFRA_66M_USB_HCK 55
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#define CLK_INFRA_66M_USB_HCK_CK_P1 56
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#define CLK_INFRA_USB_SYS_CK_P1 57
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#define CLK_INFRA_USB_CK_P1 58
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#define CLK_INFRA_USB_FRMCNT_CK_P1 59
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#define CLK_INFRA_USB_PIPE_CK_P1 60
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#define CLK_INFRA_USB_UTMI_CK_P1 61
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#define CLK_INFRA_USB_XHCI_CK_P1 62
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#define CLK_INFRA_PCIE_GFMUX_TL_P0 63
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#define CLK_INFRA_PCIE_GFMUX_TL_P1 64
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#define CLK_INFRA_PCIE_PIPE_P0 65
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#define CLK_INFRA_PCIE_PIPE_P1 66
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#define CLK_INFRA_133M_PCIE_CK_P0 67
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#define CLK_INFRA_133M_PCIE_CK_P1 68
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#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69
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#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70
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#define CLK_INFRA_NR_CLK 71
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/* TOPCKGEN */
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#define CLK_TOP_CB_M_D2 0
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#define CLK_TOP_CB_M_D3 1
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#define CLK_TOP_M_D3_D2 2
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#define CLK_TOP_CB_M_D4 3
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#define CLK_TOP_CB_M_D8 4
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#define CLK_TOP_M_D8_D2 5
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#define CLK_TOP_CB_APLL2_D4 6
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#define CLK_TOP_CB_NET1_D3 7
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#define CLK_TOP_CB_NET1_D4 8
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#define CLK_TOP_CB_NET1_D5 9
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#define CLK_TOP_NET1_D5_D2 10
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#define CLK_TOP_NET1_D5_D4 11
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#define CLK_TOP_CB_NET1_D7 12
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#define CLK_TOP_NET1_D7_D2 13
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#define CLK_TOP_NET1_D7_D4 14
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#define CLK_TOP_NET1_D8_D2 15
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#define CLK_TOP_NET1_D8_D4 16
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#define CLK_TOP_NET1_D8_D8 17
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#define CLK_TOP_NET1_D8_D16 18
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#define CLK_TOP_CB_NET2_D2 19
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#define CLK_TOP_CB_NET2_D4 20
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#define CLK_TOP_NET2_D4_D4 21
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#define CLK_TOP_NET2_D4_D8 22
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#define CLK_TOP_CB_NET2_D6 23
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#define CLK_TOP_NET2_D7_D2 24
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#define CLK_TOP_CB_NET2_D8 25
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#define CLK_TOP_MSDC_D2 26
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#define CLK_TOP_CB_CKSQ_40M 27
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#define CLK_TOP_CKSQ_40M_D2 28
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#define CLK_TOP_CB_RTC_32K 29
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#define CLK_TOP_CB_RTC_32P7K 30
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#define CLK_TOP_NETSYS_SEL 31
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#define CLK_TOP_NETSYS_500M_SEL 32
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#define CLK_TOP_NETSYS_2X_SEL 33
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#define CLK_TOP_ETH_GMII_SEL 34
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#define CLK_TOP_EIP_SEL 35
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#define CLK_TOP_AXI_INFRA_SEL 36
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#define CLK_TOP_UART_SEL 37
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#define CLK_TOP_EMMC_250M_SEL 38
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#define CLK_TOP_EMMC_400M_SEL 39
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#define CLK_TOP_SPI_SEL 40
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#define CLK_TOP_SPIM_MST_SEL 41
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#define CLK_TOP_NFI_SEL 42
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#define CLK_TOP_PWM_SEL 43
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#define CLK_TOP_I2C_SEL 44
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#define CLK_TOP_PCIE_MBIST_250M_SEL 45
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#define CLK_TOP_PEXTP_TL_SEL 46
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#define CLK_TOP_PEXTP_TL_P1_SEL 47
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#define CLK_TOP_USB_SYS_P1_SEL 48
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#define CLK_TOP_USB_XHCI_P1_SEL 49
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#define CLK_TOP_AUD_SEL 50
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#define CLK_TOP_A1SYS_SEL 51
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#define CLK_TOP_AUD_L_SEL 52
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#define CLK_TOP_A_TUNER_SEL 53
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#define CLK_TOP_USB_PHY_SEL 54
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#define CLK_TOP_SGM_0_SEL 55
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#define CLK_TOP_SGM_SBUS_0_SEL 56
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#define CLK_TOP_SGM_1_SEL 57
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#define CLK_TOP_SGM_SBUS_1_SEL 58
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#define CLK_TOP_SYSAXI_SEL 59
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#define CLK_TOP_SYSAPB_SEL 60
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#define CLK_TOP_ETH_REFCK_50M_SEL 61
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#define CLK_TOP_ETH_SYS_200M_SEL 62
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#define CLK_TOP_ETH_SYS_SEL 63
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#define CLK_TOP_ETH_XGMII_SEL 64
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#define CLK_TOP_DRAMC_SEL 65
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#define CLK_TOP_DRAMC_MD32_SEL 66
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#define CLK_TOP_INFRA_F26M_SEL 67
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#define CLK_TOP_PEXTP_P0_SEL 68
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#define CLK_TOP_PEXTP_P1_SEL 69
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#define CLK_TOP_DA_XTP_GLB_P0_SEL 70
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#define CLK_TOP_DA_XTP_GLB_P1_SEL 71
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#define CLK_TOP_CKM_SEL 72
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#define CLK_TOP_DA_CKM_XTAL_SEL 73
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#define CLK_TOP_PEXTP_SEL 74
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#define CLK_TOP_ETH_MII_SEL 75
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#define CLK_TOP_EMMC_200M_SEL 76
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#define CLK_TOP_AUD_I2S_M 77
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#define CLK_TOP_NR_CLK 78
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/* APMIXEDSYS */
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#define CLK_APMIXED_MPLL 0
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#define CLK_APMIXED_APLL2 1
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#define CLK_APMIXED_NET1PLL 2
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#define CLK_APMIXED_NET2PLL 3
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#define CLK_APMIXED_WEDMCUPLL 4
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#define CLK_APMIXED_SGMPLL 5
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#define CLK_APMIXED_ARM_LL 6
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#define CLK_APMIXED_MSDCPLL 7
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#define CLK_APMIXED_NR_CLK 8
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/* MCUSYS */
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#define CLK_MCU_BUS_DIV_SEL 0
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#define CLK_MCU_NR_CLK 1
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/* SGMIISYS_0 */
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#define CLK_SGM0_TX_EN 0
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#define CLK_SGM0_RX_EN 1
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#define CLK_SGMII0_NR_CLK 2
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/* SGMIISYS_1 */
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#define CLK_SGM1_TX_EN 0
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#define CLK_SGM1_RX_EN 1
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#define CLK_SGMII1_NR_CLK 2
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/* ETHDMA */
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#define CLK_ETHDMA_FE_EN 0
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#define CLK_ETHDMA_GP2_EN 1
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#define CLK_ETHDMA_GP1_EN 2
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#define CLK_ETHDMA_GP3_EN 3
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#define CLK_ETHDMA_NR_CLK 4
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#endif /* _DT_BINDINGS_CLK_MT7987_H */
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