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ada6328738
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also remove CONFIG_LTO=y now that there is sufficient space for SPL in
SPI flash, and to fix a build issue reported by Peter Robinson.
Fixes: 5713135ecc75 ("rockchip: rockpro64: Build u-boot-rockchip-spi.bin")
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
33 lines
512 B
Plaintext
33 lines
512 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include "rk3399-u-boot.dtsi"
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#include "rk3399-sdram-lpddr4-100.dtsi"
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/ {
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
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};
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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};
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&spi1 {
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spi_flash: flash@0 {
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bootph-all;
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};
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};
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&vdd_center {
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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&vdd_log {
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regulator-init-microvolt = <950000>;
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};
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