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120 lines
3.1 KiB
C
120 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <asm/cache.h>
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#include <asm/csr.h>
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#define CSR_MHCR 0x7c1
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#define CSR_MCOR 0x7c2
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#define CSR_MHINT 0x7c5
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#define MHCR_IE BIT(0) /* icache enable */
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#define MHCR_DE BIT(1) /* dcache enable */
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#define MHCR_WA BIT(2) /* dcache write allocate */
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#define MHCR_WB BIT(3) /* dcache write back */
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#define MHCR_RS BIT(4) /* return stack enable */
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#define MHCR_BPE BIT(5) /* branch prediction enable */
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#define MHCR_BTB BIT(6) /* branch target prediction enable */
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#define MHCR_WBR BIT(8) /* write burst enable */
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#define MHCR_L0BTB BIT(12)
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#define MCOR_CACHE_SEL_ICACHE (0x1 << 0)
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#define MCOR_CACHE_SEL_DCACHE (0x2 << 0)
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#define MCOR_CACHE_SEL_BOTH (0x3 << 0)
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#define MCOR_INV BIT(4)
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#define MCOR_CLR BIT(5)
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#define MCOR_BHT_INV BIT(16)
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#define MCOR_BTB_INV BIT(17)
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#define MHINT_DPLD BIT(2) /* dcache prefetch enable */
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#define MHINT_AMR_PAGE (0x0 << 3)
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#define MHINT_AMR_LIMIT_3 (0x1 << 3)
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#define MHINT_AMR_LIMIT_64 (0x2 << 3)
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#define MHINT_AMR_LIMIT_128 (0x3 << 3)
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#define MHINT_IPLD BIT(8) /* icache prefetch enable */
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#define MHINT_IWPE BIT(9) /* icache prediction enable */
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#define MHINT_DIS_PREFETCH_2 (0x0 << 13)
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#define MHINT_DIS_PREFETCH_4 (0x1 << 13)
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#define MHINT_DIS_PREFETCH_8 (0x2 << 13)
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#define MHINT_DIS_PREFETCH_16 (0x3 << 13)
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#define sync_i() asm volatile (".long 0x01a0000b" ::: "memory")
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void flush_dcache_all(void)
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{
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asm volatile (".long 0x0030000b" ::: "memory"); /* dcache.ciall */
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sync_i();
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (".long 0x02b5000b" ::: "memory"); /* dcache.cipa a0 */
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sync_i();
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (".long 0x0385000b" ::: "memory"); /* icache.ipa a0 */
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sync_i();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (".long 0x02a5000b" ::: "memory"); /* dcache.ipa a0 */
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sync_i();
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}
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#if 0
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void icache_enable(void)
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{
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asm volatile (".long 0x0100000b" ::: "memory"); /* icache.iall */
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sync_i();
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csr_set(CSR_MHCR, MHCR_IE | MHCR_RS | MHCR_BPE | MHCR_BTB | MHCR_L0BTB);
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csr_set(CSR_MHINT, MHINT_IPLD | MHINT_IWPE);
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}
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void icache_disable(void)
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{
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csr_clear(CSR_MHCR, MHCR_IE);
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}
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int icache_status(void)
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{
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return csr_read(CSR_MHCR) & MHCR_IE;
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}
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void dcache_enable(void)
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{
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asm volatile (".long 0x0020000b" ::: "memory"); /* dcache.iall */
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sync_i();
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csr_set(CSR_MHCR, MHCR_DE | MHCR_WA | MHCR_WB | MHCR_WBR);
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csr_set(CSR_MHINT, MHINT_DPLD | MHINT_AMR_LIMIT_3);
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}
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void dcache_disable(void)
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{
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asm volatile (".long 0x0010000b" ::: "memory"); /* dcache.call */
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sync_i();
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csr_clear(CSR_MHCR, MHCR_DE);
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}
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int dcache_status(void)
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{
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return csr_read(CSR_MHCR) & MHCR_DE;
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}
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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#endif
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