mirror of
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384 lines
8.8 KiB
C
384 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016
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* Author: Chen-Yu Tsai <wens@csie.org>
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*
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* Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
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* which was based on code by Carl van Schaik <carl@ok-labs.com>.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/cache.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cpucfg.h>
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#include <asm/arch/prcm.h>
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#include <asm/armv7.h>
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#include <asm/gic.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/system.h>
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#include <linux/bitops.h>
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#define __irq __attribute__ ((interrupt ("IRQ")))
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#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
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#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
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/*
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* R40 is different from other single cluster SoCs.
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*
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* The power clamps are located in the unused space after the per-core
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* reset controls for core 3. The secondary core entry address register
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* is in the SRAM controller address range.
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*/
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#define SUN8I_R40_PWROFF (0x110)
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#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
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#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
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static inline u32 __secure cp15_read_mpidr(void)
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{
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u32 val;
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asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
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return val;
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}
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static void __secure cp15_write_cntp_tval(u32 tval)
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{
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asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
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}
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static void __secure cp15_write_cntp_ctl(u32 val)
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{
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asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
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}
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static u32 __secure cp15_read_cntp_ctl(void)
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{
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u32 val;
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asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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return val;
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}
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#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000)
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static void __secure __mdelay(u32 ms)
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{
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u32 reg = ONE_MS * ms;
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cp15_write_cntp_tval(reg);
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isb();
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cp15_write_cntp_ctl(3);
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do {
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isb();
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reg = cp15_read_cntp_ctl();
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} while (!(reg & BIT(2)));
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cp15_write_cntp_ctl(0);
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isb();
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}
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static void __secure clamp_release(u32 __maybe_unused *clamp)
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{
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_H3) || \
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defined(CONFIG_MACH_SUN8I_R40)
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u32 tmp = 0x1ff;
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do {
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tmp >>= 1;
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writel(tmp, clamp);
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} while (tmp);
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__mdelay(10);
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#endif
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}
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static void __secure clamp_set(u32 __maybe_unused *clamp)
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{
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#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_H3) || \
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defined(CONFIG_MACH_SUN8I_R40)
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writel(0xff, clamp);
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#endif
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}
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static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
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int cpu)
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{
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if (on) {
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/* Release power clamp */
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clamp_release(clamp);
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/* Clear power gating */
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clrbits_le32(pwroff, BIT(cpu));
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} else {
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/* Set power gating */
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setbits_le32(pwroff, BIT(cpu));
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/* Activate power clamp */
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clamp_set(clamp);
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}
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}
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#ifdef CONFIG_MACH_SUN8I_R40
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/* secondary core entry address is programmed differently on R40 */
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static void __secure sunxi_set_entry_address(void *entry)
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{
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writel((u32)entry,
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SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
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}
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#elif defined CONFIG_MACH_SUN8I_T113
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static void __secure sunxi_set_entry_address(void *entry)
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{
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writel((u32)entry, 0x070005C4);
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writel((u32)entry, 0x070005C8);
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}
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#else
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static void __secure sunxi_set_entry_address(void *entry)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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writel((u32)entry, &cpucfg->priv0);
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#ifdef CONFIG_MACH_SUN8I_H3
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/* Redirect CPU 0 to the secure monitor via the resume shim. */
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writel(0x16aaefe8, &cpucfg->super_standy_flag);
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writel(0xaa16efe8, &cpucfg->super_standy_flag);
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writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
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#endif
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}
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#endif
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#ifdef CONFIG_MACH_SUN7I
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/* sun7i (A20) is different from other single cluster SoCs */
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static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
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on, 0);
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}
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#elif defined CONFIG_MACH_SUN8I_R40
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static void __secure sunxi_cpu_set_power(int cpu, bool on)
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{
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
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(void *)cpucfg + SUN8I_R40_PWROFF,
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on, cpu);
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}
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#elif defined CONFIG_MACH_SUN8I_T113
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static void __secure sunxi_cpu_set_power(int cpu, bool on)
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{
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}
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#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
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static void __secure sunxi_cpu_set_power(int cpu, bool on)
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{
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struct sunxi_prcm_reg *prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
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on, cpu);
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}
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#endif /* CONFIG_MACH_SUN7I */
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void __secure sunxi_cpu_power_off(u32 cpuid)
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{
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#ifndef CONFIG_MACH_SUN8I_T113
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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#endif
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u32 cpu = cpuid & 0x3;
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/* Wait for the core to enter WFI */
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#ifdef CONFIG_MACH_SUN8I_T113
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while (!(readl(0x9010000 + 0x80) & BIT(16 + cpu)))
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__mdelay(1);
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clrbits_le32(0x9010000, BIT(cpu));
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#else
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while (1) {
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if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
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break;
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__mdelay(1);
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}
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/* Assert reset on target CPU */
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writel(0, &cpucfg->cpu[cpu].rst);
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/* Lock CPU (Disable external debug access) */
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clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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/* Power down CPU */
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sunxi_cpu_set_power(cpuid, false);
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/* Unlock CPU (Disable external debug access) */
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setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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#endif
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}
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static u32 __secure cp15_read_scr(void)
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{
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u32 scr;
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asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
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return scr;
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}
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static void __secure cp15_write_scr(u32 scr)
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{
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asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
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isb();
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}
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/*
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* Although this is an FIQ handler, the FIQ is processed in monitor mode,
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* which means there's no FIQ banked registers. This is the same as IRQ
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* mode, so use the IRQ attribute to ask the compiler to handler entry
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* and return.
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*/
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void __secure __irq psci_fiq_enter(void)
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{
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u32 scr, reg, cpu;
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/* Switch to secure mode */
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scr = cp15_read_scr();
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cp15_write_scr(scr & ~BIT(0));
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/* Validate reason based on IAR and acknowledge */
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reg = readl(GICC_BASE + GICC_IAR);
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/* Skip spurious interrupts 1022 and 1023 */
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if (reg == 1023 || reg == 1022)
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goto out;
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/* End of interrupt */
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writel(reg, GICC_BASE + GICC_EOIR);
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dsb();
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/* Get CPU number */
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cpu = (reg >> 10) & 0x7;
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/* Power off the CPU */
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sunxi_cpu_power_off(cpu);
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out:
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/* Restore security level */
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cp15_write_scr(scr);
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}
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int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
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u32 context_id)
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{
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struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifndef CONFIG_MACH_SUN8I_T113
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struct sunxi_cpucfg_reg *cpucfg =
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(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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#endif
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u32 cpu = (mpidr & 0x3);
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u32 cpu_clk;
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u32 bus_clk;
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/* store target PC and context id */
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psci_save(cpu, pc, context_id);
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/* Set secondary core power on PC */
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sunxi_set_entry_address(&psci_cpu_entry);
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#ifdef CONFIG_MACH_SUN8I_T113
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setbits_le32(0x9010000, BIT(cpu));
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#else
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/* Assert reset on target CPU */
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writel(0, &cpucfg->cpu[cpu].rst);
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/* Invalidate L1 cache */
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clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
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/* Lock CPU (Disable external debug access) */
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clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
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/* Save registers that will be clobbered by the BROM. */
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cpu_clk = readl(&ccu->cpu_axi_cfg);
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bus_clk = readl(&ccu->ahb1_apb1_div);
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/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
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setbits_le32(&ccu->pll6_cfg, BIT(25));
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}
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/* Power up target CPU */
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sunxi_cpu_set_power(cpu, true);
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/* De-assert reset on target CPU */
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writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
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if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
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/* Spin until the BROM has clobbered the clock registers. */
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while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
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/* Restore the registers and turn off PLL_PERIPH0 bypass. */
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writel(cpu_clk, &ccu->cpu_axi_cfg);
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writel(bus_clk, &ccu->ahb1_apb1_div);
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clrbits_le32(&ccu->pll6_cfg, BIT(25));
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}
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/* Unlock CPU (Disable external debug access) */
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setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
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#endif
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return ARM_PSCI_RET_SUCCESS;
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}
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s32 __secure psci_cpu_off(void)
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{
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psci_cpu_off_common();
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if (cp15_read_mpidr() & 3) {
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/* Ask CPU0 via SGI15 to pull the rug... */
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writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
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dsb();
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} else {
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/* Unmask FIQs to service SGI15. */
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asm volatile ("cpsie f");
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}
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/* Wait to be turned off */
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while (1)
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wfi();
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}
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void __secure psci_arch_init(void)
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{
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u32 reg;
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/* SGI15 as Group-0 */
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clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
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/* Set SGI15 priority to 0 */
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writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
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/* Be cool with non-secure */
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writel(0xff, GICC_BASE + GICC_PMR);
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/* Switch FIQEn on */
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setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
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reg = cp15_read_scr();
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reg |= BIT(2); /* Enable FIQ in monitor mode */
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reg &= ~BIT(0); /* Secure mode */
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cp15_write_scr(reg);
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}
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