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	This change introduces a reset controller driver for SCMI agent devices. When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent binds a reset controller device for each SCMI reset domain protocol devices enabled in the FDT. SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Reset Domain protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
		
			
				
	
	
		
			180 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			180 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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| /*
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|  * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
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|  * Copyright (C) 2019-2020, Linaro Limited
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|  */
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| #ifndef _SCMI_PROTOCOLS_H
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| #define _SCMI_PROTOCOLS_H
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| 
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| #include <linux/bitops.h>
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| #include <asm/types.h>
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| 
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| /*
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|  * Subset the SCMI protocols definition
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|  * based on SCMI specification v2.0 (DEN0056B)
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|  * https://developer.arm.com/docs/den0056/b
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|  */
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| 
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| enum scmi_std_protocol {
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| 	SCMI_PROTOCOL_ID_BASE = 0x10,
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| 	SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
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| 	SCMI_PROTOCOL_ID_SYSTEM = 0x12,
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| 	SCMI_PROTOCOL_ID_PERF = 0x13,
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| 	SCMI_PROTOCOL_ID_CLOCK = 0x14,
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| 	SCMI_PROTOCOL_ID_SENSOR = 0x15,
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| 	SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
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| };
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| 
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| enum scmi_status_code {
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| 	SCMI_SUCCESS =  0,
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| 	SCMI_NOT_SUPPORTED = -1,
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| 	SCMI_INVALID_PARAMETERS = -2,
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| 	SCMI_DENIED = -3,
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| 	SCMI_NOT_FOUND = -4,
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| 	SCMI_OUT_OF_RANGE = -5,
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| 	SCMI_BUSY = -6,
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| 	SCMI_COMMS_ERROR = -7,
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| 	SCMI_GENERIC_ERROR = -8,
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| 	SCMI_HARDWARE_ERROR = -9,
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| 	SCMI_PROTOCOL_ERROR = -10,
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| };
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| 
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| /*
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|  * SCMI Clock Protocol
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|  */
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| 
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| enum scmi_clock_message_id {
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| 	SCMI_CLOCK_RATE_SET = 0x5,
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| 	SCMI_CLOCK_RATE_GET = 0x6,
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| 	SCMI_CLOCK_CONFIG_SET = 0x7,
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| };
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| 
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| #define SCMI_CLK_RATE_ASYNC_NOTIFY	BIT(0)
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| #define SCMI_CLK_RATE_ASYNC_NORESP	(BIT(0) | BIT(1))
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| #define SCMI_CLK_RATE_ROUND_DOWN	0
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| #define SCMI_CLK_RATE_ROUND_UP		BIT(2)
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| #define SCMI_CLK_RATE_ROUND_CLOSEST	BIT(3)
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| 
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| /**
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|  * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command
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|  * @clock_id:	SCMI clock ID
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|  * @attributes:	Attributes of the targets clock state
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|  */
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| struct scmi_clk_state_in {
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| 	u32 clock_id;
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| 	u32 attributes;
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| };
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| 
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| /**
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|  * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command
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|  * @status:	SCMI command status
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|  */
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| struct scmi_clk_state_out {
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| 	s32 status;
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| };
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| 
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| /**
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|  * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command
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|  * @clock_id:	SCMI clock ID
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|  * @attributes:	Attributes of the targets clock state
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|  */
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| struct scmi_clk_rate_get_in {
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| 	u32 clock_id;
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| };
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| 
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| /**
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|  * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command
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|  * @status:	SCMI command status
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|  * @rate_lsb:	32bit LSB of the clock rate in Hertz
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|  * @rate_msb:	32bit MSB of the clock rate in Hertz
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|  */
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| struct scmi_clk_rate_get_out {
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| 	s32 status;
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| 	u32 rate_lsb;
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| 	u32 rate_msb;
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| };
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| 
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| /**
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|  * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command
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|  * @clock_id:	SCMI clock ID
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|  * @flags:	Flags for the clock rate set request
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|  * @rate_lsb:	32bit LSB of the clock rate in Hertz
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|  * @rate_msb:	32bit MSB of the clock rate in Hertz
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|  */
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| struct scmi_clk_rate_set_in {
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| 	u32 clock_id;
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| 	u32 flags;
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| 	u32 rate_lsb;
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| 	u32 rate_msb;
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| };
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| 
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| /**
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|  * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command
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|  * @status:	SCMI command status
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|  */
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| struct scmi_clk_rate_set_out {
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| 	s32 status;
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| };
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| 
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| /*
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|  * SCMI Reset Domain Protocol
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|  */
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| 
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| enum scmi_reset_domain_message_id {
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| 	SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3,
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| 	SCMI_RESET_DOMAIN_RESET = 0x4,
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| };
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| 
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| #define SCMI_RD_NAME_LEN		16
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| 
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| #define SCMI_RD_ATTRIBUTES_FLAG_ASYNC	BIT(31)
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| #define SCMI_RD_ATTRIBUTES_FLAG_NOTIF	BIT(30)
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| 
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| #define SCMI_RD_RESET_FLAG_ASYNC	BIT(2)
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| #define SCMI_RD_RESET_FLAG_ASSERT	BIT(1)
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| #define SCMI_RD_RESET_FLAG_CYCLE	BIT(0)
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| 
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| /**
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|  * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message
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|  * @domain_id:	SCMI reset domain ID
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|  */
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| struct scmi_rd_attr_in {
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| 	u32 domain_id;
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| };
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| 
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| /**
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|  * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response
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|  * @status:	SCMI command status
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|  * @attributes:	Retrieved attributes of the reset domain
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|  * @latency:	Reset cycle max lantency
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|  * @name:	Reset domain name
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|  */
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| struct scmi_rd_attr_out {
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| 	s32 status;
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| 	u32 attributes;
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| 	u32 latency;
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| 	char name[SCMI_RD_NAME_LEN];
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| };
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| 
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| /**
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|  * struct scmi_rd_reset_in - Message payload for RESET command
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|  * @domain_id:		SCMI reset domain ID
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|  * @flags:		Flags for the reset request
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|  * @reset_state:	Reset target state
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|  */
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| struct scmi_rd_reset_in {
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| 	u32 domain_id;
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| 	u32 flags;
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| 	u32 reset_state;
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| };
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| 
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| /**
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|  * struct scmi_rd_reset_out - Response payload for RESET command
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|  * @status:	SCMI command status
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|  */
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| struct scmi_rd_reset_out {
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| 	s32 status;
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| };
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| 
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| #endif /* _SCMI_PROTOCOLS_H */
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