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4939beea8e
Synchronize device tree bindings with v5.5-rc6 tag with commit id "b3a987b0264d". Also, it removes older clock binding defined for S900 along with undocumented compatible string "actions,s900-serial" from serial driver and adapts clock driver to cater to new bindings. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
334 lines
8.1 KiB
Plaintext
334 lines
8.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Andreas Färber
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*/
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#include <dt-bindings/clock/actions,s900-cmu.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/actions,s900-reset.h>
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/ {
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compatible = "actions,s900";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@1f000000 {
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reg = <0x0 0x1f000000 0x0 0x1000000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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hosc: hosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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losc: losc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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diff24M: diff24M {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@e00f1000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe00f1000 0x0 0x1000>,
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<0x0 0xe00f2000 0x0 0x2000>,
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<0x0 0xe00f4000 0x0 0x2000>,
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<0x0 0xe00f6000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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uart0: serial@e0120000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0120000 0x0 0x2000>;
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clocks = <&cmu CLK_UART0>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@e0122000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0122000 0x0 0x2000>;
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clocks = <&cmu CLK_UART1>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart2: serial@e0124000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0124000 0x0 0x2000>;
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clocks = <&cmu CLK_UART2>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart3: serial@e0126000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0126000 0x0 0x2000>;
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clocks = <&cmu CLK_UART3>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@e0128000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0128000 0x0 0x2000>;
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clocks = <&cmu CLK_UART4>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart5: serial@e012a000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012a000 0x0 0x2000>;
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clocks = <&cmu CLK_UART5>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart6: serial@e012c000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012c000 0x0 0x2000>;
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clocks = <&cmu CLK_UART6>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sps: power-controller@e012e000 {
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compatible = "actions,s900-sps";
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reg = <0x0 0xe012e000 0x0 0x2000>;
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#power-domain-cells = <1>;
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};
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cmu: clock-controller@e0160000 {
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compatible = "actions,s900-cmu";
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reg = <0x0 0xe0160000 0x0 0x1000>;
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clocks = <&hosc>, <&losc>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2c0: i2c@e0170000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe0170000 0 0x1000>;
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clocks = <&cmu CLK_I2C0>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@e0172000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe0172000 0 0x1000>;
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clocks = <&cmu CLK_I2C1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@e0174000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe0174000 0 0x1000>;
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clocks = <&cmu CLK_I2C2>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@e0176000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe0176000 0 0x1000>;
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clocks = <&cmu CLK_I2C3>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@e0178000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe0178000 0 0x1000>;
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clocks = <&cmu CLK_I2C4>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@e017a000 {
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compatible = "actions,s900-i2c";
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reg = <0 0xe017a000 0 0x1000>;
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clocks = <&cmu CLK_I2C5>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s900-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 146>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer: timer@e0228000 {
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compatible = "actions,s900-timer";
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reg = <0x0 0xe0228000 0x0 0x8000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "timer1";
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};
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dma: dma-controller@e0260000 {
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compatible = "actions,s900-dma";
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reg = <0x0 0xe0260000 0x0 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <12>;
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dma-requests = <46>;
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clocks = <&cmu CLK_DMAC>;
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};
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mmc0: mmc@e0330000 {
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compatible = "actions,owl-mmc";
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reg = <0x0 0xe0330000 0x0 0x4000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD0>;
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resets = <&cmu RESET_SD0>;
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dmas = <&dma 2>;
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dma-names = "mmc";
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status = "disabled";
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};
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mmc1: mmc@e0334000 {
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compatible = "actions,owl-mmc";
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reg = <0x0 0xe0334000 0x0 0x4000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD1>;
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resets = <&cmu RESET_SD1>;
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dmas = <&dma 3>;
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dma-names = "mmc";
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status = "disabled";
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};
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mmc2: mmc@e0338000 {
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compatible = "actions,owl-mmc";
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reg = <0x0 0xe0338000 0x0 0x4000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD2>;
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resets = <&cmu RESET_SD2>;
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dmas = <&dma 4>;
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dma-names = "mmc";
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status = "disabled";
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};
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mmc3: mmc@e033c000 {
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compatible = "actions,owl-mmc";
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reg = <0x0 0xe033c000 0x0 0x4000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD3>;
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resets = <&cmu RESET_SD3>;
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dmas = <&dma 46>;
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dma-names = "mmc";
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status = "disabled";
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};
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};
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};
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