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https://github.com/smaeul/u-boot.git
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
211 lines
6.7 KiB
C
211 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Header file for the Marvell's Feroceon CPU core.
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*/
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#ifndef _MVEBU_SOC_H
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#define _MVEBU_SOC_H
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define SOC_MV78230_ID 0x7823
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#define SOC_MV78260_ID 0x7826
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#define SOC_MV78460_ID 0x7846
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#define SOC_88F6720_ID 0x6720
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#define SOC_88F6810_ID 0x6810
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#define SOC_88F6820_ID 0x6820
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#define SOC_88F6828_ID 0x6828
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#define SOC_98DX3236_ID 0xf410
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#define SOC_98DX3336_ID 0xf400
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#define SOC_98DX4251_ID 0xfc00
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/* A375 revisions */
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#define MV_88F67XX_A0_ID 0x3
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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#define MV_88F68XX_B0_ID 0xa
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/* TCLK Core Clock definition */
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#ifndef CONFIG_SYS_TCLK
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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#endif
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
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/*
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* The SPL U-Boot version still runs with the default
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* address for the internal registers, configured by
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* the BootROM. Only the main U-Boot version uses the
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* new internal register base address, that also is
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* required for the Linux kernel.
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*/
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#define SOC_REGS_PHY_BASE 0xd0000000
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#elif defined(CONFIG_ARMADA_8K)
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#define SOC_REGS_PHY_BASE 0xf0000000
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#else
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#define SOC_REGS_PHY_BASE 0xf1000000
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#endif
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
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#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
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#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
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#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
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#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
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#define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700))
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#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
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#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
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#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
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#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
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#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
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#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
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#define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000))
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#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
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#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
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#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
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#ifdef CONFIG_ARMADA_MSYS
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#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
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#else
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#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
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#endif
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#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
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#define MBUS_ERR_PROP_EN (1 << 8)
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#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
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#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
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#define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08)
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#define NAND_EN BIT(0)
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#define NAND_ARBITER_EN BIT(27)
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#define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c)
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#define GE0_PUP_EN BIT(0)
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#define GE1_PUP_EN BIT(1)
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#define LCD_PUP_EN BIT(2)
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#define NAND_PUP_EN BIT(4)
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#define SPI_PUP_EN BIT(5)
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#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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#ifdef CONFIG_ARMADA_MSYS
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#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
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#define NAND_ECC_DIVCKL_RATIO_OFFS 6
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#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
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#else
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#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
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#endif
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#ifdef CONFIG_ARMADA_MSYS
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#define NAND_ECC_DIVCKL_RATIO_OFFS 6
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#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
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#else
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#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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#endif
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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/* MVEBU CPU memory windows */
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#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
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#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
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#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
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#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
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/* BootROM error register (also includes some status infos) */
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#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
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#define BOOTROM_ERR_MODE_OFFS 28
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#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
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#define BOOTROM_ERR_MODE_UART 0x6
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#define BOOTROM_ERR_CODE_OFFS 0
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#define BOOTROM_ERR_CODE_MASK (0xf << BOOTROM_ERR_CODE_OFFS)
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#if defined(CONFIG_ARMADA_375)
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/* SAR values for Armada 375 */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204))
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#define SAR_CPU_FREQ_OFFS 17
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define BOOT_DEV_SEL_OFFS 3
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#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_UART 0x30
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#define BOOT_FROM_SPI 0x38
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#elif defined(CONFIG_ARMADA_38X)
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/* SAR values for Armada 38x */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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#define SAR_CPU_FREQ_OFFS 10
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 4
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#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
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#define BOOT_DEV_SEL_OFFS 4
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#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_NAND 0x0A
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#define BOOT_FROM_SATA 0x22
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#define BOOT_FROM_UART 0x28
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#define BOOT_FROM_SATA_ALT 0x2A
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#define BOOT_FROM_UART_ALT 0x3f
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#define BOOT_FROM_SPI 0x32
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#define BOOT_FROM_MMC 0x30
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#define BOOT_FROM_MMC_ALT 0x31
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#elif defined(CONFIG_ARMADA_MSYS)
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/* SAR values for MSYS */
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#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
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#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
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#define SAR_CPU_FREQ_OFFS 18
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 11
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#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
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#define BOOT_DEV_SEL_OFFS 11
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#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_NAND 0x1
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#define BOOT_FROM_UART 0x2
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#define BOOT_FROM_SPI 0x3
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#else
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/* SAR values for Armada XP */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_FFC_FREQ_OFFS 24
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#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
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#define SAR2_CPU_FREQ_OFFS 20
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#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 5
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#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
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#define BOOT_DEV_SEL_OFFS 5
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#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_UART 0x2
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#define BOOT_FROM_SPI 0x3
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#endif
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#endif /* _MVEBU_SOC_H */
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