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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
107 lines
2.2 KiB
C
107 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fsl_pmic.h>
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#include <i2c.h>
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#include <asm/global_data.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int mc34708_reg_count(struct udevice *dev)
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{
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return PMIC_NUM_OF_REGS;
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}
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static int mc34708_write(struct udevice *dev, uint reg, const u8 *buff,
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int len)
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{
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u8 buf[3] = { 0 };
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int ret;
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if (len != MC34708_TRANSFER_SIZE)
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return -EINVAL;
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/*
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* The MC34708 sends data with big endian format, hence we need to
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* perform manual byte swap.
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*/
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buf[0] = buff[2];
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buf[1] = buff[1];
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buf[2] = buff[0];
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ret = dm_i2c_write(dev, reg, buf, len);
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if (ret)
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printf("write error to device: %p register: %#x!\n", dev, reg);
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return ret;
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}
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static int mc34708_read(struct udevice *dev, uint reg, u8 *buff, int len)
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{
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u8 buf[3] = { 0 };
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int ret;
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if (len != MC34708_TRANSFER_SIZE)
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return -EINVAL;
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ret = dm_i2c_read(dev, reg, buf, len);
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if (ret)
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printf("read error from device: %p register: %#x!\n", dev, reg);
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buff[0] = buf[2];
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buff[1] = buf[1];
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buff[2] = buf[0];
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return ret;
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}
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static int mc34708_probe(struct udevice *dev)
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{
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struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
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priv->trans_len = MC34708_TRANSFER_SIZE;
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/*
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* Handle PMIC Errata 37: APS mode not fully functional,
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* use explicit PWM or PFM instead
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*/
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pmic_clrsetbits(dev, MC34708_REG_SW12_OPMODE,
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MC34708_SW1AMODE_MASK | MC34708_SW2MODE_MASK,
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SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 14u));
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pmic_clrsetbits(dev, MC34708_REG_SW345_OPMODE,
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MC34708_SW3MODE_MASK | MC34708_SW4AMODE_MASK |
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MC34708_SW4BMODE_MASK | MC34708_SW5MODE_MASK,
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SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 6u) |
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(SW_MODE_PWMPWM << 12u) | (SW_MODE_PWMPWM << 18u));
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return 0;
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}
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static struct dm_pmic_ops mc34708_ops = {
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.reg_count = mc34708_reg_count,
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.read = mc34708_read,
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.write = mc34708_write,
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};
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static const struct udevice_id mc34708_ids[] = {
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{ .compatible = "fsl,mc34708" },
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{ }
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};
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U_BOOT_DRIVER(pmic_mc34708) = {
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.name = "mc34708_pmic",
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.id = UCLASS_PMIC,
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.of_match = mc34708_ids,
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.probe = mc34708_probe,
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.ops = &mc34708_ops,
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};
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