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2bd58608db
New timer structure and defines will move to new timer.h Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
112 lines
4.3 KiB
C
112 lines
4.3 KiB
C
/*
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* mcftimer.h -- ColdFire internal TIMER support defines.
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*
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* Based on mcftimer.h of uCLinux distribution:
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* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************/
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#ifndef mcftimer_h
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#define mcftimer_h
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/****************************************************************************/
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#include <linux/config.h>
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/*
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* Get address specific defines for this ColdFire member.
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*/
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#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
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#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
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#elif defined(CONFIG_M5272)
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#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
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#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
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#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
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#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
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#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
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#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
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#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
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#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
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#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
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#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
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#endif
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/*
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* Define the TIMER register set addresses.
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*/
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#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
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#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
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#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
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#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
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#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
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/*
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* Define the TIMER register set addresses for 5282.
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*/
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#define MCFTIMER_PCSR 0
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#define MCFTIMER_PMR 1
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#define MCFTIMER_PCNTR 2
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/*
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* Bit definitions for the Timer Mode Register (TMR).
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* Register bit flags are common accross ColdFires.
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*/
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#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
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#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
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#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
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#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
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#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
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#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
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#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
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#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
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#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
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#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
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#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
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#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
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#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
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#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
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#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
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#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
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#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
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/*
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* Bit definitions for the Timer Event Registers (TER).
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*/
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#define MCFTIMER_TER_CAP 0x01 /* Capture event */
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#define MCFTIMER_TER_REF 0x02 /* Refernece event */
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/*
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* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
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*/
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#define MCFTIMER_PCSR_EN 0x0001
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#define MCFTIMER_PCSR_RLD 0x0002
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#define MCFTIMER_PCSR_PIF 0x0004
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#define MCFTIMER_PCSR_PIE 0x0008
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#define MCFTIMER_PCSR_OVW 0x0010
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#define MCFTIMER_PCSR_HALTED 0x0020
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#define MCFTIMER_PCSR_DOZE 0x0040
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/****************************************************************************/
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#endif /* mcftimer_h */
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