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https://github.com/smaeul/u-boot.git
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2ab02fd456
According to schematics and to RedBoot sources, the MX31ADS uses a 32768Hz oscillator as a SKIL source. Fix previously wrongly assumed 32000Hz value. Also fix a typo when verifying a jumper configuration. While at it, make two needlessly global functions static. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
282 lines
7.1 KiB
ArmAsm
282 lines
7.1 KiB
ArmAsm
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/mx31-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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/* RedBoot: AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =0x43F00000
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ldr r1, =0x77777777
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =0x53F00000
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =0x43F00000
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ldr r1, =0x0
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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ldr r1, [r0, #0x50]
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and r1, r1, #0x00FFFFFF
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str r1, [r0, #0x50]
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ldr r0, =0x53F00000
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ldr r1, =0x0
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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ldr r1, [r0, #0x50]
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and r1, r1, #0x00FFFFFF
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str r1, [r0, #0x50]
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.endm /* init_aips */
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/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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ldr r0, =0x43F04000
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =0x00302154
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =0x10
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =0x0
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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.endm /* init_max */
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/* RedBoot: M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =0xB8003000
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =0x00000040
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str r0, [r1] /* M3IF control reg */
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.endm /* init_m3if */
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/* RedBoot: To support 133MHz DDR */
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.macro init_drive_strength
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/*
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* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
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* in SW_PAD_CTL registers
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*/
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/* SDCLK */
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ldr r1, =0x43FAC200
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ldr r0, [r1, #0x6C]
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bic r0, r0, #(1 << 12)
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str r0, [r1, #0x6C]
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/* CAS */
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ldr r0, [r1, #0x70]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x70]
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/* RAS */
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ldr r0, [r1, #0x74]
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bic r0, r0, #(1 << 2)
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str r0, [r1, #0x74]
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/* CS2 (CSD0) */
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ldr r0, [r1, #0x7C]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x7C]
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/* DQM3 */
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ldr r0, [r1, #0x84]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x84]
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/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
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ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
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pad_loop:
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ldr r0, [r1, #0x88]
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bic r0, r0, #(1 << 22)
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bic r0, r0, #(1 << 12)
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bic r0, r0, #(1 << 2)
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str r0, [r1, #0x88]
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add r1, r1, #4
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subs r2, r2, #0x1
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bne pad_loop
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.endm /* init_drive_strength */
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/* CPLD on CS4 setup */
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.macro init_cs4
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ldr r0, =WEIM_BASE
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ldr r1, =0x0000D843
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str r1, [r0, #0x40]
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ldr r1, =0x22252521
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str r1, [r0, #0x44]
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ldr r1, =0x22220A00
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str r1, [r0, #0x48]
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.endm /* init_cs4 */
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.globl lowlevel_init
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lowlevel_init:
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/* Redboot initializes very early AIPS, what for?
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF */
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =0x40000015 /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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init_aips
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init_max
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init_m3if
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init_drive_strength
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init_cs4
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/* Image Processing Unit: */
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/* Too early to switch display on? */
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REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
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/* Clock Control Module: */
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REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
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/* PBC CPLD on CS4 */
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mov r1, #CS4_BASE
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ldrh r1, [r1, #0x2]
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/* Is 27MHz switch set? */
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ands r1, r1, #0x10
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/* 532-133-66.5 */
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ldr r0, =CCM_BASE
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ldr r1, =0xFF871D58
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/* PDR0 */
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str r1, [r0, #0x4]
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ldreq r1, MPCTL_PARAM_532
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ldrne r1, MPCTL_PARAM_532_27
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/* MPCTL */
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str r1, [r0, #0x10]
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/* Set UPLL=240MHz, USB=60MHz */
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ldr r1, =0x49FCFE7F
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/* PDR1 */
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str r1, [r0, #0x8]
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ldreq r1, UPCTL_PARAM_240
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ldrne r1, UPCTL_PARAM_240_27
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/* UPCTL */
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str r1, [r0, #0x14]
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/* default CLKO to 1/8 of the ARM core */
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mov r1, #0x000002C0
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add r1, r1, #0x00000006
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/* COSR */
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str r1, [r0, #0x1c]
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/* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
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/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
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/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
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/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
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/* Default: 1, 4, 12, 1 */
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
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REG 0xB8001010, 0x00000004
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REG 0xB8001004, 0x006ac73a
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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REG 0xB8001000, 0x82226080
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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mov pc, lr
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MPCTL_PARAM_532:
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.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
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MPCTL_PARAM_532_27:
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.word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
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UPCTL_PARAM_240:
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.word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
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UPCTL_PARAM_240_27:
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.word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
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