mirror of
https://github.com/smaeul/u-boot.git
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8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
310 lines
8.2 KiB
C
310 lines
8.2 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <pci.h>
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#include "hardware.h"
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#include "pcippc2.h"
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struct pci_controller local_hose, cpci_hose;
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static u32 cpc710_mapped_ram;
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/* Enable PCI retry timeouts
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*/
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void cpc710_pci_enable_timeout (void)
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{
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out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
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iobarrier_rw();
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}
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void cpc710_pci_init (void)
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{
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u32 sdram_size = pcippc2_sdram_size();
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cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
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sdram_size : PCI_MEMORY_MAXSIZE;
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/* Select the local PCI
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*/
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out32(REG(CPC0, PCICNFR), 0x80000002);
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iobarrier_rw();
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out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
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iobarrier_rw();
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/* Enable PCI bridge address decoding
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*/
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out32(REG(CPC0, PCIENB), 0x80000000);
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iobarrier_rw();
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/* Select the CPCI bridge
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*/
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out32(REG(CPC0, PCICNFR), 0x80000003);
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iobarrier_rw();
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out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
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iobarrier_rw();
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/* Enable PCI bridge address decoding
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*/
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out32(REG(CPC0, PCIENB), 0x80000000);
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iobarrier_rw();
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/* Disable configuration accesses
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*/
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out32(REG(CPC0, PCICNFR), 0x80000000);
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iobarrier_rw();
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/* Initialise the local PCI
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*/
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out32(BRIDGE(LOCAL, CRR), 0x7c000000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
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out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
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out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
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out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
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out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, PR), 0x00ffe000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, ACR), 0xfe000000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
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out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
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out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
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iobarrier_rw();
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/* Initialise the CPCI bridge
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*/
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out32(BRIDGE(CPCI, CRR), 0x7c000000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
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out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
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out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
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iobarrier_rw();
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out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
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out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
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out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
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iobarrier_rw();
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out32(BRIDGE(CPCI, PR), 0x80ffe000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, ACR), 0xdf000000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
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out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
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out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
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iobarrier_rw();
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/* Local PCI
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*/
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out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
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iobarrier_rw();
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/* Set bus and subbus numbers
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*/
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out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
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iobarrier_rw();
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out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
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iobarrier_rw();
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/* PCI retry timeouts will be enabled later
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*/
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out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
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iobarrier_rw();
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/* CPCI
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*/
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/* Set bus and subbus numbers
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*/
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out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
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iobarrier_rw();
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/* Write to the PSBAR */
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out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
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iobarrier_rw();
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/* Set bus and subbus numbers
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*/
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out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
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/* PCI retry timeouts will be enabled later
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*/
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out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
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iobarrier_rw();
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/* Remove reset on the PCI buses
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*/
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out32(BRIDGE(LOCAL, CRR), 0xfc000000);
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iobarrier_rw();
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out32(BRIDGE(CPCI, CRR), 0xfc000000);
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iobarrier_rw();
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local_hose.first_busno = 0;
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local_hose.last_busno = 0xff;
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/* System memory space */
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pci_set_region(local_hose.regions + 0,
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PCI_MEMORY_BUS,
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PCI_MEMORY_PHYS,
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PCI_MEMORY_MAXSIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(local_hose.regions + 1,
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BRIDGE_LOCAL_MEM_BUS,
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BRIDGE_LOCAL_MEM_PHYS,
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BRIDGE_LOCAL_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(local_hose.regions + 2,
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BRIDGE_LOCAL_IO_BUS,
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BRIDGE_LOCAL_IO_PHYS,
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BRIDGE_LOCAL_IO_SIZE,
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PCI_REGION_IO);
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local_hose.region_count = 3;
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pci_setup_indirect(&local_hose,
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BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
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BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
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pci_register_hose(&local_hose);
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/* Initialize PCI32 bus registers */
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pci_hose_write_config_byte(&local_hose,
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PCI_BDF(local_hose.first_busno,0,0),
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CPC710_BUS_NUMBER,
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local_hose.first_busno);
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pci_hose_write_config_byte(&local_hose,
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PCI_BDF(local_hose.first_busno,0,0),
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CPC710_SUB_BUS_NUMBER,
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local_hose.last_busno);
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local_hose.last_busno = pci_hose_scan(&local_hose);
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/* Write out correct max subordinate bus number for local hose */
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pci_hose_write_config_byte(&local_hose,
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PCI_BDF(local_hose.first_busno,0,0),
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CPC710_SUB_BUS_NUMBER,
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local_hose.last_busno);
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cpci_hose.first_busno = local_hose.last_busno + 1;
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cpci_hose.last_busno = 0xff;
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/* System memory space */
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pci_set_region(cpci_hose.regions + 0,
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PCI_MEMORY_BUS,
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PCI_MEMORY_PHYS,
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PCI_MEMORY_MAXSIZE,
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PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(cpci_hose.regions + 1,
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BRIDGE_CPCI_MEM_BUS,
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BRIDGE_CPCI_MEM_PHYS,
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BRIDGE_CPCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(cpci_hose.regions + 2,
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BRIDGE_CPCI_IO_BUS,
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BRIDGE_CPCI_IO_PHYS,
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BRIDGE_CPCI_IO_SIZE,
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PCI_REGION_IO);
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cpci_hose.region_count = 3;
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pci_setup_indirect(&cpci_hose,
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BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
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BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
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pci_register_hose(&cpci_hose);
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/* Initialize PCI64 bus registers */
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pci_hose_write_config_byte(&cpci_hose,
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PCI_BDF(cpci_hose.first_busno,0,0),
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CPC710_BUS_NUMBER,
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cpci_hose.first_busno);
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pci_hose_write_config_byte(&cpci_hose,
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PCI_BDF(cpci_hose.first_busno,0,0),
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CPC710_SUB_BUS_NUMBER,
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cpci_hose.last_busno);
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cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
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/* Write out correct max subordinate bus number for cpci hose */
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pci_hose_write_config_byte(&cpci_hose,
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PCI_BDF(cpci_hose.first_busno,0,0),
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CPC710_SUB_BUS_NUMBER,
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cpci_hose.last_busno);
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}
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