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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
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*/
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#ifndef _SYSTEM_MANAGER_ARRIA10_H_
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#define _SYSTEM_MANAGER_ARRIA10_H_
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#define SYSMGR_A10_WDDBG 0x08
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#define SYSMGR_A10_BOOTINFO 0x0c
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#define SYSMGR_A10_DMA 0x20
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#define SYSMGR_A10_DMA_PERIPH 0x24
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#define SYSMGR_A10_SDMMC 0x28
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#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
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#define SYSMGR_A10_EMAC_GLOBAL 0x40
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#define SYSMGR_A10_EMAC0 0x44
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#define SYSMGR_A10_EMAC1 0x48
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#define SYSMGR_A10_EMAC2 0x4c
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#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
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#define SYSMGR_A10_FPGAINTF_EN0 0x64
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#define SYSMGR_A10_FPGAINTF_EN1 0x68
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#define SYSMGR_A10_FPGAINTF_EN2 0x6c
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#define SYSMGR_A10_FPGAINTF_EN3 0x70
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#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
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#define SYSMGR_A10_ECC_INTMASK_SET 0x94
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#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
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#define SYSMGR_A10_NOC_TIMEOUT 0xc0
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#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
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#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
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#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
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#define SYSMGR_A10_NOC_IDLEACK 0xd0
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#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
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#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
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#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
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#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
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