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0008e9a69d
Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
251 lines
8.7 KiB
C
251 lines
8.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef NIC_REG_H
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#define NIC_REG_H
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#define NIC_PF_REG_COUNT 29573
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#define NIC_VF_REG_COUNT 249
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/* Physical function register offsets */
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#define NIC_PF_CFG (0x0000)
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#define NIC_PF_STATUS (0x0010)
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#define NIC_PF_INTR_TIMER_CFG (0x0030)
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#define NIC_PF_BIST_STATUS (0x0040)
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#define NIC_PF_SOFT_RESET (0x0050)
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#define NIC_PF_TCP_TIMER (0x0060)
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#define NIC_PF_BP_CFG (0x0080)
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#define NIC_PF_RRM_CFG (0x0088)
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#define NIC_PF_CQM_CF (0x00A0)
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#define NIC_PF_CNM_CF (0x00A8)
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#define NIC_PF_CNM_STATUS (0x00B0)
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#define NIC_PF_CQ_AVG_CFG (0x00C0)
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#define NIC_PF_RRM_AVG_CFG (0x00C8)
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#define NIC_PF_INTF_0_1_SEND_CFG (0x0200)
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#define NIC_PF_INTF_0_1_BP_CFG (0x0208)
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#define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210)
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#define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220)
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#define NIC_PF_RBDR_BP_STATE_0_3 (0x0240)
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#define NIC_PF_MAILBOX_INT (0x0410)
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#define NIC_PF_MAILBOX_INT_W1S (0x0430)
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#define NIC_PF_MAILBOX_ENA_W1C (0x0450)
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#define NIC_PF_MAILBOX_ENA_W1S (0x0470)
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#define NIC_PF_RX_ETYPE_0_7 (0x0500)
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#define NIC_PF_RX_CFG (0x05D0)
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#define NIC_PF_PKIND_0_15_CFG (0x0600)
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#define NIC_PF_ECC0_FLIP0 (0x1000)
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#define NIC_PF_ECC1_FLIP0 (0x1008)
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#define NIC_PF_ECC2_FLIP0 (0x1010)
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#define NIC_PF_ECC3_FLIP0 (0x1018)
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#define NIC_PF_ECC0_FLIP1 (0x1080)
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#define NIC_PF_ECC1_FLIP1 (0x1088)
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#define NIC_PF_ECC2_FLIP1 (0x1090)
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#define NIC_PF_ECC3_FLIP1 (0x1098)
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#define NIC_PF_ECC0_CDIS (0x1100)
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#define NIC_PF_ECC1_CDIS (0x1108)
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#define NIC_PF_ECC2_CDIS (0x1110)
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#define NIC_PF_ECC3_CDIS (0x1118)
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#define NIC_PF_BIST0_STATUS (0x1280)
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#define NIC_PF_BIST1_STATUS (0x1288)
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#define NIC_PF_BIST2_STATUS (0x1290)
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#define NIC_PF_BIST3_STATUS (0x1298)
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#define NIC_PF_ECC0_SBE_INT (0x2000)
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#define NIC_PF_ECC0_SBE_INT_W1S (0x2008)
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#define NIC_PF_ECC0_SBE_ENA_W1C (0x2010)
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#define NIC_PF_ECC0_SBE_ENA_W1S (0x2018)
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#define NIC_PF_ECC0_DBE_INT (0x2100)
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#define NIC_PF_ECC0_DBE_INT_W1S (0x2108)
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#define NIC_PF_ECC0_DBE_ENA_W1C (0x2110)
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#define NIC_PF_ECC0_DBE_ENA_W1S (0x2118)
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#define NIC_PF_ECC1_SBE_INT (0x2200)
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#define NIC_PF_ECC1_SBE_INT_W1S (0x2208)
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#define NIC_PF_ECC1_SBE_ENA_W1C (0x2210)
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#define NIC_PF_ECC1_SBE_ENA_W1S (0x2218)
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#define NIC_PF_ECC1_DBE_INT (0x2300)
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#define NIC_PF_ECC1_DBE_INT_W1S (0x2308)
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#define NIC_PF_ECC1_DBE_ENA_W1C (0x2310)
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#define NIC_PF_ECC1_DBE_ENA_W1S (0x2318)
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#define NIC_PF_ECC2_SBE_INT (0x2400)
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#define NIC_PF_ECC2_SBE_INT_W1S (0x2408)
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#define NIC_PF_ECC2_SBE_ENA_W1C (0x2410)
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#define NIC_PF_ECC2_SBE_ENA_W1S (0x2418)
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#define NIC_PF_ECC2_DBE_INT (0x2500)
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#define NIC_PF_ECC2_DBE_INT_W1S (0x2508)
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#define NIC_PF_ECC2_DBE_ENA_W1C (0x2510)
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#define NIC_PF_ECC2_DBE_ENA_W1S (0x2518)
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#define NIC_PF_ECC3_SBE_INT (0x2600)
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#define NIC_PF_ECC3_SBE_INT_W1S (0x2608)
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#define NIC_PF_ECC3_SBE_ENA_W1C (0x2610)
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#define NIC_PF_ECC3_SBE_ENA_W1S (0x2618)
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#define NIC_PF_ECC3_DBE_INT (0x2700)
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#define NIC_PF_ECC3_DBE_INT_W1S (0x2708)
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#define NIC_PF_ECC3_DBE_ENA_W1C (0x2710)
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#define NIC_PF_ECC3_DBE_ENA_W1S (0x2718)
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#define NIC_PF_CPI_0_2047_CFG (0x200000)
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#define NIC_PF_MPI_0_2047_CFG (0x210000)
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#define NIC_PF_RSSI_0_4097_RQ (0x220000)
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#define NIC_PF_LMAC_0_7_CFG (0x240000)
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#define NIC_PF_LMAC_0_7_SW_XOFF (0x242000)
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#define NIC_PF_LMAC_0_7_CREDIT (0x244000)
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#define NIC_PF_CHAN_0_255_TX_CFG (0x400000)
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#define NIC_PF_CHAN_0_255_RX_CFG (0x420000)
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#define NIC_PF_CHAN_0_255_SW_XOFF (0x440000)
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#define NIC_PF_CHAN_0_255_CREDIT (0x460000)
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#define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000)
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#define NIC_PF_SW_SYNC_RX (0x490000)
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#define NIC_PF_SW_SYNC_RX_DONE (0x490008)
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#define NIC_PF_TL2_0_63_CFG (0x500000)
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#define NIC_PF_TL2_0_63_PRI (0x520000)
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#define NIC_PF_TL2_LMAC (0x540000)
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#define NIC_PF_TL2_0_63_SH_STATUS (0x580000)
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#define NIC_PF_TL3A_0_63_CFG (0x5F0000)
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#define NIC_PF_TL3_0_255_CFG (0x600000)
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#define NIC_PF_TL3_0_255_CHAN (0x620000)
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#define NIC_PF_TL3_0_255_PIR (0x640000)
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#define NIC_PF_TL3_0_255_SW_XOFF (0x660000)
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#define NIC_PF_TL3_0_255_CNM_RATE (0x680000)
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#define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000)
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#define NIC_PF_TL4A_0_255_CFG (0x6F0000)
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#define NIC_PF_TL4_0_1023_CFG (0x800000)
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#define NIC_PF_TL4_0_1023_SW_XOFF (0x820000)
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#define NIC_PF_TL4_0_1023_SH_STATUS (0x840000)
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#define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000)
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#define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000)
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#define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030)
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#define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000)
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#define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100)
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#define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000)
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#define NIC_PF_QSET_0_127_CFG (0x20010000)
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#define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400)
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#define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420)
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#define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500)
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#define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600)
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#define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00)
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#define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08)
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#define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00)
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#define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000)
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#define NIC_PF_MSIX_VEC_0_CTL (0x000008)
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#define NIC_PF_MSIX_PBA_0 (0x0F0000)
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/* Virtual function register offsets */
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#define NIC_VNIC_CFG (0x000020)
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#define NIC_VF_PF_MAILBOX_0_1 (0x000130)
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#define NIC_VF_INT (0x000200)
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#define NIC_VF_INT_W1S (0x000220)
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#define NIC_VF_ENA_W1C (0x000240)
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#define NIC_VF_ENA_W1S (0x000260)
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#define NIC_VNIC_RSS_CFG (0x0020E0)
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#define NIC_VNIC_RSS_KEY_0_4 (0x002200)
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#define NIC_VNIC_TX_STAT_0_4 (0x004000)
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#define NIC_VNIC_RX_STAT_0_13 (0x004100)
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#define NIC_QSET_RQ_GEN_CFG (0x010010)
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#define NIC_QSET_CQ_0_7_CFG (0x010400)
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#define NIC_QSET_CQ_0_7_CFG2 (0x010408)
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#define NIC_QSET_CQ_0_7_THRESH (0x010410)
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#define NIC_QSET_CQ_0_7_BASE (0x010420)
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#define NIC_QSET_CQ_0_7_HEAD (0x010428)
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#define NIC_QSET_CQ_0_7_TAIL (0x010430)
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#define NIC_QSET_CQ_0_7_DOOR (0x010438)
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#define NIC_QSET_CQ_0_7_STATUS (0x010440)
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#define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
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#define NIC_QSET_CQ_0_7_DEBUG (0x010450)
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#define NIC_QSET_RQ_0_7_CFG (0x010600)
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#define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700)
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#define NIC_QSET_SQ_0_7_CFG (0x010800)
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#define NIC_QSET_SQ_0_7_THRESH (0x010810)
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#define NIC_QSET_SQ_0_7_BASE (0x010820)
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#define NIC_QSET_SQ_0_7_HEAD (0x010828)
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#define NIC_QSET_SQ_0_7_TAIL (0x010830)
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#define NIC_QSET_SQ_0_7_DOOR (0x010838)
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#define NIC_QSET_SQ_0_7_STATUS (0x010840)
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#define NIC_QSET_SQ_0_7_DEBUG (0x010848)
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#define NIC_QSET_SQ_0_7_CNM_CHG (0x010860)
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#define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900)
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#define NIC_QSET_RBDR_0_1_CFG (0x010C00)
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#define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
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#define NIC_QSET_RBDR_0_1_BASE (0x010C20)
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#define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
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#define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
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#define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
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#define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
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#define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
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#define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50)
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#define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000)
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#define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008)
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#define NIC_VF_MSIX_PBA (0x0F0000)
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/* Offsets within registers */
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#define NIC_MSIX_VEC_SHIFT 4
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#define NIC_Q_NUM_SHIFT 18
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#define NIC_QS_ID_SHIFT 21
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#define NIC_VF_NUM_SHIFT 21
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/* Port kind configuration register */
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struct pkind_cfg {
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#if defined(__BIG_ENDIAN_BITFIELD)
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uint64_t reserved_42_63:22;
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uint64_t hdr_sl:5; /* Header skip length */
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uint64_t rx_hdr:3; /* TNS Receive header present */
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uint64_t lenerr_en:1; /* L2 length error check enable */
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uint64_t reserved_32_32:1;
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uint64_t maxlen:16; /* Max frame size */
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uint64_t minlen:16; /* Min frame size */
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#elif defined(__LITTLE_ENDIAN_BITFIELD)
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uint64_t minlen:16;
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uint64_t maxlen:16;
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uint64_t reserved_32_32:1;
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uint64_t lenerr_en:1;
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uint64_t rx_hdr:3;
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uint64_t hdr_sl:5;
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uint64_t reserved_42_63:22;
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#endif
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};
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static inline uint64_t BGXX_PF_BAR0(unsigned long param1)
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__attribute__ ((pure, always_inline));
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static inline uint64_t BGXX_PF_BAR0(unsigned long param1)
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{
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assert(param1 <= 1);
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return 0x87E0E0000000 + (param1 << 24);
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}
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#define BGXX_PF_BAR0_SIZE 0x400000
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#define NIC_PF_BAR0 0x843000000000
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#define NIC_PF_BAR0_SIZE 0x40000000
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static inline uint64_t NIC_VFX_BAR0(unsigned long param1)
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__attribute__ ((pure, always_inline));
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static inline uint64_t NIC_VFX_BAR0(unsigned long param1)
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{
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assert(param1 <= 127);
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return 0x8430A0000000 + (param1 << 21);
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}
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#define NIC_VFX_BAR0_SIZE 0x200000
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#endif /* NIC_REG_H */
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