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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include <asm/io.h>
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#include <asm/cpu_common.h>
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#include <asm/fast_spi.h>
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#include <asm/pci.h>
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/*
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* Returns bios_start and fills in size of the BIOS region.
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*/
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static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
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uint *bios_size)
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{
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ulong bios_start, bios_end;
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/*
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* BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
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* Limit. Base and Limit fields are in units of 4K.
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*/
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u32 val = readl(®s->bfp);
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bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12;
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bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
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SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12;
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*bios_size = bios_end - bios_start;
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return bios_start;
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}
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int fast_spi_get_bios_mmap_regs(struct fast_spi_regs *regs, ulong *map_basep,
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uint *map_sizep, uint *offsetp)
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{
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ulong base;
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base = fast_spi_get_bios_region(regs, map_sizep);
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*map_basep = (u32)-*map_sizep - base;
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*offsetp = base;
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return 0;
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}
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int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
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uint *offsetp)
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{
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struct fast_spi_regs *regs;
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ulong bar, mmio_base;
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/* Special case to find mapping without probing the device */
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pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
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mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
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regs = (struct fast_spi_regs *)mmio_base;
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return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep, offsetp);
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}
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int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
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{
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/* Program Temporary BAR for SPI */
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0,
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mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY,
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PCI_SIZE_32);
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/* Enable Bus Master and MMIO Space */
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pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY, PCI_SIZE_8);
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/*
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* Disable the BIOS write protect so write commands are allowed.
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* Enable Prefetching and caching.
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*/
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pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL,
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SPIBAR_BIOS_CONTROL_EISS |
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SPIBAR_BIOS_CONTROL_CACHE_DISABLE,
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SPIBAR_BIOS_CONTROL_WPD |
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SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8);
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return 0;
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}
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