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The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
146 lines
3.9 KiB
Plaintext
146 lines
3.9 KiB
Plaintext
Overview
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--------
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P2020RDB is a Low End Dual core platform supporting the P2020 processor
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of QorIQ series. P2020 is an e500 based dual core SOC.
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Building U-boot
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-----------
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To build the u-boot for P2020RDB:
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make P2020RDB_config
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make
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NOR Flash Banks
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-----------
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RDB board for P2020 has two flash banks. They are both present on boot.
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Booting by default is always from the boot bank at 0xef00_0000.
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Memory Map
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----------
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0xef00_0000 - 0xef7f_ffff Alernate bank 8MB
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0xe800_0000 - 0xefff_ffff Boot bank 8MB
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0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
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0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
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Switch settings to boot from the NOR flash banks
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------------------------------------------------
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SW4[8]=0 default NOR Flash bank
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SW4[8]=1 Alternate NOR Flash bank
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Flashing Images
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---------------
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To place a new u-boot image in the alternate flash bank and then boot
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with that new image temporarily, use this:
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tftp 1000000 u-boot.bin
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erase ef780000 ef7fffff
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cp.b 1000000 ef780000 80000
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Now to boot from the alternate bank change the SW4[8] from 0 to 1.
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To program the image in the boot flash bank:
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tftp 1000000 u-boot.bin
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protect off all
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erase eff80000 ffffffff
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cp.b 1000000 eff80000 80000
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage.p2020rdb
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp c00000 p2020rdb.dtb
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bootm 1000000 2000000 c00000
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Implementing AMP(Asymmetric MultiProcessing)
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---------------------------------------------
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1. Build kernel image for core0:
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a. $ make 85xx/p1_p2_rdb_defconfig
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b. $ make menuconfig
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- un-select "Processor support"->
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"Symetric multi-processing support"
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c. $ make uImage
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
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2. Build kernel image for core1:
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a. $ make 85xx/p1_p2_rdb_defconfig
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b. $ make menuconfig
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- Un-select "Processor support"->
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"Symetric multi-processing support"
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- Select "Advanced setup" ->
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"Prompt for advanced kernel configuration options"
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- Select
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"Set physical address where the kernel is loaded"
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and set it to 0x20000000, asssuming core1 will
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start from 512MB.
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- Select "Set custom page offset address"
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- Select "Set custom kernel base address"
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- Select "Set maximum low memory"
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- "Exit" and save the selection.
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c. $ make uImage
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d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
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3. Create dtb for core0:
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$ dtc -I dts -O dtb -f -b 0
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arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
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/tftpboot/p2020rdb_camp_core0.dtb
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4. Create dtb for core1:
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$ dtc -I dts -O dtb -f -b 1
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arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
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/tftpboot/p2020rdb_camp_core1.dtb
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5. Bring up two cores separately:
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a. Power on the board, under u-boot prompt:
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=> setenv <serverip>
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=> setenv <ipaddr>
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=> setenv bootargs root=/dev/ram rw console=ttyS0,115200
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b. Bring up core1's kernel first:
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=> setenv bootm_low 0x20000000
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=> setenv bootm_size 0x10000000
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=> tftp 21000000 uImage.core1
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=> tftp 22000000 ramdiskfile
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=> tftp 20c00000 p2020rdb_camp_core1.dtb
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=> interrupts off
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=> bootm start 21000000 22000000 20c00000
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=> bootm loados
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=> bootm ramdisk
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=> bootm fdt
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=> fdt boardsetup
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=> fdt chosen $initrd_start $initrd_end
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=> bootm prep
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=> cpu 1 release $bootm_low - $fdtaddr -
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c. Bring up core0's kernel(on the same u-boot console):
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=> setenv bootm_low 0
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=> setenv bootm_size 0x20000000
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=> tftp 1000000 uImage.core0
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=> tftp 2000000 ramdiskfile
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=> tftp c00000 p2020rdb_camp_core0.dtb
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=> bootm 1000000 2000000 c00000
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Please note only core0 will run u-boot, core1 starts kernel directly
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after "cpu release" command is issued.
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