mirror of
https://github.com/smaeul/u-boot.git
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9395eb05ee
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
147 lines
3.2 KiB
C
147 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <env.h>
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#include <init.h>
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#include <malloc.h>
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#include <errno.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/clock.h>
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#include <linux/delay.h>
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#include <spl.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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int board_phys_sdram_size(phys_size_t *size)
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{
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int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
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if (ddr_size == 0x4) {
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*size = 0x100000000;
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} else if (ddr_size == 0x3) {
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*size = 0xc0000000;
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} else if (ddr_size == 0x2) {
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*size = 0x80000000;
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} else if (ddr_size == 0x1) {
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*size = 0x40000000;
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} else {
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printf("Unknown DDR type!!!\n");
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return -1;
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}
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return 0;
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}
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#ifdef CONFIG_FEC_MXC
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#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
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#define FEC_PWR_PAD IMX_GPIO_NR(1, 0)
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static iomux_v3_cfg_t const fec1_pads[] = {
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/* Reset */
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IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Power */
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IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr");
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gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
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udelay(500);
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gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
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gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
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udelay(500);
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gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_fec();
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_rev", "iMX8MQ");
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#endif
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return 0;
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}
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