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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
875 lines
25 KiB
C
875 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek clock driver for MT8512 SoC
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*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Chen Zhong <chen.zhong@mediatek.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/mt8512-clk.h>
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#include <linux/bitops.h>
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#include "clk-mtk.h"
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#define MT8512_PLL_FMAX (3800UL * MHZ)
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#define MT8512_PLL_FMIN (1500UL * MHZ)
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#define MT8512_CON0_RST_BAR BIT(23)
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/* apmixedsys */
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#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
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_pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
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.id = _id, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.rst_bar_mask = MT8512_CON0_RST_BAR, \
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.fmax = MT8512_PLL_FMAX, \
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.fmin = MT8512_PLL_FMIN, \
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.flags = _flags, \
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.pcwbits = _pcwbits, \
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.pcwibits = 8, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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}
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static const struct mtk_pll_data apmixed_plls[] = {
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PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
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0, 22, 0x0310, 24, 0x0310, 0, 0),
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PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
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HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
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PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
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HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
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PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
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0, 22, 0x0354, 24, 0x0354, 0, 0),
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PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
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0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
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PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
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0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
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PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
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0, 22, 0x0378, 24, 0x0378, 0, 0),
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PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
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0, 22, 0x0394, 24, 0x0394, 0, 0),
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PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
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0, 22, 0x03A4, 24, 0x03A4, 0, 0),
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};
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/* topckgen */
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#define FACTOR0(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
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#define FACTOR1(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
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#define FACTOR2(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, 0)
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static const struct mtk_fixed_clk top_fixed_clks[] = {
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FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
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FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
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};
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static const struct mtk_fixed_factor top_fixed_divs[] = {
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FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
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FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
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FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
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FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
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FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
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FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
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FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
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FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
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FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
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FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
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FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
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FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
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FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
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FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
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FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
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FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
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FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
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FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
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FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
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FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
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FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
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FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
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FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
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FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
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FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
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FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
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FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
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FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
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FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
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FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
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FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
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FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
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FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
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FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
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FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
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FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
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FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
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FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
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FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
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FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
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FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
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FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
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FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
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FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
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FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
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FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
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FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
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FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
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FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
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FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
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FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
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FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
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FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
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FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
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FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
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FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
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};
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static const int axi_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_UNIVPLL3_D2,
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CLK_TOP_SYSPLL1_D8,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_CLK32K
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};
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static const int mem_parents[] = {
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CLK_TOP_DSPPLL,
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CLK_TOP_IPPLL,
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL_D3
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};
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static const int uart_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D8
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};
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static const int spi_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_SYSPLL2_D2,
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CLK_TOP_UNIVPLL1_D4,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_UNIVPLL3_D2,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_SYSPLL4_D2
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};
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static const int spis_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL_D3,
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CLK_TOP_SYSPLL_D3,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_UNIVPLL1_D4,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_SYSPLL4_D2
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};
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static const int msdc50_0_hc_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_UNIVPLL1_D4,
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CLK_TOP_SYSPLL2_D2
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};
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static const int msdc50_0_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_MSDCPLL_D2,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_SYSPLL2_D2,
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CLK_TOP_UNIVPLL1_D4,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_SYSPLL2_D4,
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CLK_TOP_UNIVPLL2_D8
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};
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static const int msdc50_2_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_MSDCPLL,
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CLK_TOP_UNIVPLL_D3,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_SYSPLL2_D2,
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CLK_TOP_UNIVPLL1_D4
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};
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static const int audio_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D8,
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CLK_TOP_APLL1_D4,
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CLK_TOP_APLL2_D4
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};
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static const int aud_intbus_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL1_D4,
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CLK_TOP_UNIVPLL3_D2,
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CLK_TOP_APLL2_D8,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_APLL1_D8,
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CLK_TOP_UNIVPLL3_D4
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};
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static const int hapll1_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_APLL1,
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CLK_TOP_APLL1_D2,
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CLK_TOP_APLL1_D3,
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CLK_TOP_APLL1_D4,
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CLK_TOP_APLL1_D8,
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CLK_TOP_APLL1_D16,
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CLK_TOP_SYS_26M_D2
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};
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static const int hapll2_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_APLL2,
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CLK_TOP_APLL2_D2,
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CLK_TOP_APLL2_D3,
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CLK_TOP_APLL2_D4,
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CLK_TOP_APLL2_D8,
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CLK_TOP_APLL2_D16,
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CLK_TOP_SYS_26M_D2
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};
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static const int asm_l_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_SYSPLL_D5
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};
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static const int aud_spdif_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL_D2,
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CLK_TOP_DSPPLL
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};
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static const int aud_1_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_APLL1
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};
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static const int aud_2_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_APLL2
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};
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static const int ssusb_sys_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL3_D2
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};
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static const int spm_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL1_D8
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};
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static const int i2c_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_UNIVPLL3_D2,
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CLK_TOP_SYSPLL1_D8,
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CLK_TOP_SYSPLL2_D8,
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CLK_TOP_CLK32K
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};
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static const int pwm_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_SYSPLL1_D8,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_CLK32K
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};
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static const int dsp_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_DSPPLL,
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CLK_TOP_DSPPLL_D2,
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CLK_TOP_DSPPLL_D4,
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CLK_TOP_DSPPLL_D8,
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CLK_TOP_APLL2_D4,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_CLK32K
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};
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static const int nfi2x_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL2_D2,
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CLK_TOP_SYSPLL_D7,
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CLK_TOP_SYSPLL_D3,
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CLK_TOP_SYSPLL2_D4,
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CLK_TOP_MSDCPLL_D2,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_UNIVPLL_D5
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};
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static const int spinfi_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D8,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_SYSPLL1_D8,
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CLK_TOP_SYSPLL4_D2,
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CLK_TOP_SYSPLL2_D4,
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CLK_TOP_UNIVPLL2_D4,
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CLK_TOP_UNIVPLL3_D2
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};
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static const int ecc_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL_D5,
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CLK_TOP_SYSPLL_D3,
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CLK_TOP_UNIVPLL_D3
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};
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static const int gcpu_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL_D3,
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CLK_TOP_SYSPLL_D3,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_UNIVPLL2_D2
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};
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static const int gcpu_cpm_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_SYSPLL2_D2,
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CLK_TOP_UNIVPLL1_D4
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};
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static const int mbist_diag_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYS_26M_D2
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};
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static const int ip0_nna_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_DSPPLL,
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CLK_TOP_DSPPLL_D2,
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CLK_TOP_DSPPLL_D4,
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CLK_TOP_IPPLL,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_IPPLL_D2,
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CLK_TOP_MSDCPLL_D2
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};
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static const int ip2_wfst_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_UNIVPLL_D3,
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CLK_TOP_UNIVPLL1_D2,
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CLK_TOP_UNIVPLL2_D2,
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CLK_TOP_IPPLL,
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CLK_TOP_IPPLL_D2,
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CLK_TOP_SYS_26M_D2,
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CLK_TOP_MSDCPLL
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};
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static const int sflash_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_SYSPLL1_D16,
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CLK_TOP_SYSPLL2_D8,
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CLK_TOP_SYSPLL3_D4,
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CLK_TOP_UNIVPLL3_D4,
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CLK_TOP_UNIVPLL1_D8,
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CLK_TOP_USB20_192M_D2,
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CLK_TOP_UNIVPLL2_D4
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};
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static const int sram_parents[] = {
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CLK_TOP_CLK26M,
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CLK_TOP_DSPPLL,
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CLK_TOP_UNIVPLL_D3,
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CLK_TOP_SYSPLL1_D2,
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CLK_TOP_APLL1,
|
|
CLK_TOP_APLL2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_SYS_26M_D2
|
|
};
|
|
|
|
static const int mm_parents[] = {
|
|
CLK_TOP_CLK26M,
|
|
CLK_TOP_SYSPLL_D3,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL_D5,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_UNIVPLL_D3
|
|
};
|
|
|
|
static const int dpi0_parents[] = {
|
|
CLK_TOP_CLK26M,
|
|
CLK_TOP_TCONPLL_D2,
|
|
CLK_TOP_TCONPLL_D4,
|
|
CLK_TOP_TCONPLL_D8,
|
|
CLK_TOP_TCONPLL_D16,
|
|
CLK_TOP_TCONPLL_D32,
|
|
CLK_TOP_TCONPLL_D64
|
|
};
|
|
|
|
static const int dbg_atclk_parents[] = {
|
|
CLK_TOP_CLK26M,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_UNIVPLL_D5
|
|
};
|
|
|
|
static const int occ_104m_parents[] = {
|
|
CLK_TOP_UNIVPLL2_D4,
|
|
CLK_TOP_UNIVPLL2_D8
|
|
};
|
|
|
|
static const int occ_68m_parents[] = {
|
|
CLK_TOP_SYSPLL1_D8,
|
|
CLK_TOP_UNIVPLL2_D8
|
|
};
|
|
|
|
static const int occ_182m_parents[] = {
|
|
CLK_TOP_SYSPLL2_D2,
|
|
CLK_TOP_UNIVPLL1_D4,
|
|
CLK_TOP_UNIVPLL2_D8
|
|
};
|
|
|
|
static const struct mtk_composite top_muxes[] = {
|
|
/* CLK_CFG_0 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
|
|
0x040, 0x044, 0x048, 0, 3, 7,
|
|
0x4, 0, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
|
|
0x040, 0x044, 0x048, 8, 2, 15,
|
|
0x4, 1, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
|
|
0x040, 0x044, 0x048, 16, 1, 23,
|
|
0x4, 2, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
|
|
0x040, 0x044, 0x048, 24, 3, 31,
|
|
0x4, 3, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_1 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
|
|
0x050, 0x054, 0x058, 0, 3, 7,
|
|
0x4, 4, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
|
|
0x050, 0x054, 0x058, 8, 2, 15,
|
|
0x4, 5, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
|
|
0x050, 0x054, 0x058, 16, 2, 23,
|
|
0x4, 6, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
|
|
0x050, 0x054, 0x058, 24, 3, 31,
|
|
0x4, 7, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_2 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
|
|
0x060, 0x064, 0x068, 0, 3, 7,
|
|
0x4, 8, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
|
|
0x060, 0x064, 0x068, 8, 3, 15,
|
|
0x4, 9, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
|
|
0x060, 0x064, 0x068, 16, 2, 23,
|
|
0x4, 10, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
|
|
0x060, 0x064, 0x068, 24, 3, 31,
|
|
0x4, 11, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_3 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
|
|
0x070, 0x074, 0x078, 0, 3, 7,
|
|
0x4, 12, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
|
|
0x070, 0x074, 0x078, 8, 3, 15,
|
|
0x4, 13, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
|
|
0x070, 0x074, 0x078, 16, 3, 23,
|
|
0x4, 14, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
|
|
0x070, 0x074, 0x078, 24, 3, 31,
|
|
0x4, 15, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_4 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
|
|
0x080, 0x084, 0x088, 0, 2, 7,
|
|
0x4, 16, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
|
|
0x080, 0x084, 0x088, 8, 2, 15,
|
|
0x4, 17, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
|
|
0x080, 0x084, 0x088, 16, 2, 23,
|
|
0x4, 18, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
|
|
0x080, 0x084, 0x088, 24, 2, 31,
|
|
0x4, 19, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_5 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
|
|
0x090, 0x094, 0x098, 0, 1, 7,
|
|
0x4, 20, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
|
|
0x090, 0x094, 0x098, 8, 1, 15,
|
|
0x4, 21, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
|
|
0x090, 0x094, 0x098, 16, 2, 23,
|
|
0x4, 22, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
|
|
0x090, 0x094, 0x098, 24, 2, 31,
|
|
0x4, 23, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_6 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
|
|
0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
|
|
0x4, 24, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
|
|
0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
|
|
0x4, 25, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
|
|
0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
|
|
0x4, 26, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
|
|
0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
|
|
0x4, 27, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_7 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
|
|
0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
|
|
0x4, 28, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
|
|
0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
|
|
0x4, 29, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
|
|
0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
|
|
0x4, 30, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
|
|
0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
|
|
0x4, 31, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_8 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
|
|
0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
|
|
0x8, 0, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
|
|
0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
|
|
0x8, 1, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
|
|
0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
|
|
0x8, 2, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
|
|
0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
|
|
0x8, 3, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_9 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
|
|
0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
|
|
0x8, 4, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
|
|
0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
|
|
0x8, 5, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
|
|
0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
|
|
0x8, 6, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
|
|
0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
|
|
0x8, 7, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_10 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
|
|
0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
|
|
0x8, 8, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
|
|
0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
|
|
0x8, 9, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
|
|
0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
|
|
0x8, 10, CLK_MUX_SETCLR_UPD),
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
|
|
0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
|
|
0x8, 11, CLK_MUX_SETCLR_UPD),
|
|
/* CLK_CFG_11 */
|
|
MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
|
|
0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
|
|
0x8, 12, CLK_MUX_SETCLR_UPD),
|
|
};
|
|
|
|
static const struct mtk_gate_regs top0_cg_regs = {
|
|
.set_ofs = 0x0,
|
|
.clr_ofs = 0x0,
|
|
.sta_ofs = 0x0,
|
|
};
|
|
|
|
static const struct mtk_gate_regs top1_cg_regs = {
|
|
.set_ofs = 0x104,
|
|
.clr_ofs = 0x104,
|
|
.sta_ofs = 0x104,
|
|
};
|
|
|
|
#define GATE_TOP0(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &top0_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_TOP1(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &top1_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
static const struct mtk_gate top_clks[] = {
|
|
/* TOP0 */
|
|
GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
|
|
GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
|
|
GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
|
|
GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
|
|
/* TOP1 */
|
|
GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
|
|
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
|
|
GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
|
|
GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra0_cg_regs = {
|
|
.set_ofs = 0x294,
|
|
.clr_ofs = 0x294,
|
|
.sta_ofs = 0x294,
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra1_cg_regs = {
|
|
.set_ofs = 0x80,
|
|
.clr_ofs = 0x84,
|
|
.sta_ofs = 0x90,
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra2_cg_regs = {
|
|
.set_ofs = 0x88,
|
|
.clr_ofs = 0x8c,
|
|
.sta_ofs = 0x94,
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra3_cg_regs = {
|
|
.set_ofs = 0xa4,
|
|
.clr_ofs = 0xa8,
|
|
.sta_ofs = 0xac,
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra4_cg_regs = {
|
|
.set_ofs = 0xc0,
|
|
.clr_ofs = 0xc4,
|
|
.sta_ofs = 0xc8,
|
|
};
|
|
|
|
static const struct mtk_gate_regs infra5_cg_regs = {
|
|
.set_ofs = 0xd0,
|
|
.clr_ofs = 0xd4,
|
|
.sta_ofs = 0xd8,
|
|
};
|
|
|
|
#define GATE_INFRA0(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra0_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_INFRA1(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra1_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_INFRA2(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra2_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_INFRA3(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra3_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_INFRA4(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra4_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
#define GATE_INFRA5(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra5_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
static const struct mtk_gate infra_clks[] = {
|
|
/* INFRA0 */
|
|
GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
|
|
/* INFRA1 */
|
|
GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
|
|
GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
|
|
GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
|
|
GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
|
|
GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
|
|
GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
|
|
GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
|
|
GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
|
|
GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
|
|
GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
|
|
GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
|
|
GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
|
|
GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
|
|
GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
|
|
GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
|
|
GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
|
|
GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
|
|
GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
|
|
/* INFRA2 */
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GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
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GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
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GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
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GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
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GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
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GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
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GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
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GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
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GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
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GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
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GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
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GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
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/* INFRA3 */
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GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
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GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
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GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
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GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
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GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
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GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
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/* INFRA4 */
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GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
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GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
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GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
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GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
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GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
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GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
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GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
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GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
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GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
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/* INFRA5 */
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GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
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GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
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GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
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GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
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GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
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GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
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};
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static const struct mtk_clk_tree mt8512_clk_tree = {
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.xtal_rate = 26 * MHZ,
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.xtal2_rate = 26 * MHZ,
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.fdivs_offs = CLK_TOP_SYSPLL1_D2,
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.muxes_offs = CLK_TOP_AXI_SEL,
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.plls = apmixed_plls,
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.fclks = top_fixed_clks,
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.fdivs = top_fixed_divs,
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.muxes = top_muxes,
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};
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static int mt8512_apmixedsys_probe(struct udevice *dev)
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{
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return mtk_common_clk_init(dev, &mt8512_clk_tree);
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}
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static int mt8512_topckgen_probe(struct udevice *dev)
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{
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return mtk_common_clk_init(dev, &mt8512_clk_tree);
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}
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static int mt8512_topckgen_cg_probe(struct udevice *dev)
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{
|
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return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
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}
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static int mt8512_infracfg_probe(struct udevice *dev)
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{
|
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return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
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}
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|
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static const struct udevice_id mt8512_apmixed_compat[] = {
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{ .compatible = "mediatek,mt8512-apmixedsys", },
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{ }
|
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};
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static const struct udevice_id mt8512_topckgen_compat[] = {
|
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{ .compatible = "mediatek,mt8512-topckgen", },
|
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{ }
|
|
};
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|
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static const struct udevice_id mt8512_topckgen_cg_compat[] = {
|
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{ .compatible = "mediatek,mt8512-topckgen-cg", },
|
|
{ }
|
|
};
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|
|
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static const struct udevice_id mt8512_infracfg_compat[] = {
|
|
{ .compatible = "mediatek,mt8512-infracfg", },
|
|
{ }
|
|
};
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|
|
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U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
|
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.name = "mt8512-apmixedsys",
|
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.id = UCLASS_CLK,
|
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.of_match = mt8512_apmixed_compat,
|
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.probe = mt8512_apmixedsys_probe,
|
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.priv_auto = sizeof(struct mtk_clk_priv),
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.ops = &mtk_clk_apmixedsys_ops,
|
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.flags = DM_FLAG_PRE_RELOC,
|
|
};
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|
|
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U_BOOT_DRIVER(mtk_clk_topckgen) = {
|
|
.name = "mt8512-topckgen",
|
|
.id = UCLASS_CLK,
|
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.of_match = mt8512_topckgen_compat,
|
|
.probe = mt8512_topckgen_probe,
|
|
.priv_auto = sizeof(struct mtk_clk_priv),
|
|
.ops = &mtk_clk_topckgen_ops,
|
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.flags = DM_FLAG_PRE_RELOC,
|
|
};
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|
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U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
|
|
.name = "mt8512-topckgen-cg",
|
|
.id = UCLASS_CLK,
|
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.of_match = mt8512_topckgen_cg_compat,
|
|
.probe = mt8512_topckgen_cg_probe,
|
|
.priv_auto = sizeof(struct mtk_cg_priv),
|
|
.ops = &mtk_clk_gate_ops,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|
|
|
|
U_BOOT_DRIVER(mtk_clk_infracfg) = {
|
|
.name = "mt8512-infracfg",
|
|
.id = UCLASS_CLK,
|
|
.of_match = mt8512_infracfg_compat,
|
|
.probe = mt8512_infracfg_probe,
|
|
.priv_auto = sizeof(struct mtk_cg_priv),
|
|
.ops = &mtk_clk_gate_ops,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
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