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https://github.com/smaeul/u-boot.git
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b0db69b4e1
Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
94 lines
2.0 KiB
C
94 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI gate clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/gate.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <linux/clk-provider.h>
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struct clk_ti_gate_priv {
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fdt_addr_t reg;
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u8 enable_bit;
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u32 flags;
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bool invert_enable;
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};
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static int clk_ti_gate_disable(struct clk *clk)
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{
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struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
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u32 v;
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v = readl(priv->reg);
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if (priv->invert_enable)
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v |= (1 << priv->enable_bit);
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else
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v &= ~(1 << priv->enable_bit);
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writel(v, priv->reg);
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/* No OCP barrier needed here since it is a disable operation */
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return 0;
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}
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static int clk_ti_gate_enable(struct clk *clk)
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{
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struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
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u32 v;
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v = readl(priv->reg);
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if (priv->invert_enable)
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v &= ~(1 << priv->enable_bit);
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else
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v |= (1 << priv->enable_bit);
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writel(v, priv->reg);
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/* OCP barrier */
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v = readl(priv->reg);
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return 0;
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}
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static int clk_ti_gate_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_gate_priv *priv = dev_get_priv(dev);
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priv->reg = dev_read_addr(dev);
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if (priv->reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "failed to get control register\n");
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return -EINVAL;
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}
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dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
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priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
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if (dev_read_bool(dev, "ti,set-rate-parent"))
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priv->flags |= CLK_SET_RATE_PARENT;
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priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable");
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return 0;
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}
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static struct clk_ops clk_ti_gate_ops = {
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.enable = clk_ti_gate_enable,
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.disable = clk_ti_gate_disable,
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};
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static const struct udevice_id clk_ti_gate_of_match[] = {
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{ .compatible = "ti,gate-clock" },
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{ },
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};
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U_BOOT_DRIVER(clk_ti_gate) = {
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.name = "ti_gate_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_gate_of_match,
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.of_to_plat = clk_ti_gate_of_to_plat,
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.priv_auto = sizeof(struct clk_ti_gate_priv),
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.ops = &clk_ti_gate_ops,
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};
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