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7f92c3a275
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet_serdes.h"
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
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SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
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NONE, NONE, AURORA, AURORA},
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[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
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SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
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[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
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SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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[0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
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AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
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SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
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SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
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};
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
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{
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if (!serdes_lane_enabled(lane))
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return NONE;
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(u32 prtcl)
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{
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int i;
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if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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void soc_serdes_init(void)
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{
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/*
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* On the P3060 the devdisr2 register does not correctly reflect
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* the state of the MACs based on the RCW fields. So disable the MACs
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* based on the srds_prtcl and ec1, ec2, ec3 fields
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*/
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
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/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
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if (!is_serdes_configured(SGMII_FM1_DTSEC3))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
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if (!is_serdes_configured(SGMII_FM1_DTSEC4))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
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if (!is_serdes_configured(SGMII_FM2_DTSEC1))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
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if (!is_serdes_configured(SGMII_FM2_DTSEC2))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
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if (!is_serdes_configured(SGMII_FM2_DTSEC3))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
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if (!is_serdes_configured(SGMII_FM2_DTSEC4))
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devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
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if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
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}
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if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
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devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
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}
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out_be32(&gur->devdisr2, devdisr2);
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}
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