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d8d29a4489
Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
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*/
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#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
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#define _DT_BINDINGS_STM32MP1_RESET_H_
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#define MCU_HOLD_BOOT_R 2144
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#define LTDC_R 3072
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#define DSI_R 3076
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#define DDRPERFM_R 3080
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#define USBPHY_R 3088
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#define SPI6_R 3136
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#define I2C4_R 3138
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#define I2C6_R 3139
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#define USART1_R 3140
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#define STGEN_R 3156
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#define GPIOZ_R 3200
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#define CRYP1_R 3204
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#define HASH1_R 3205
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#define RNG1_R 3206
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#define AXIM_R 3216
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#define GPU_R 3269
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#define ETHMAC_R 3274
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#define FMC_R 3276
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#define QSPI_R 3278
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#define SDMMC1_R 3280
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#define SDMMC2_R 3281
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#define CRC1_R 3284
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#define USBH_R 3288
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#define MDMA_R 3328
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#define MCU_R 8225
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#define TIM2_R 19456
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#define TIM3_R 19457
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#define TIM4_R 19458
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#define TIM5_R 19459
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#define TIM6_R 19460
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#define TIM7_R 19461
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#define TIM12_R 16462
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#define TIM13_R 16463
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#define TIM14_R 16464
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#define LPTIM1_R 19465
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#define SPI2_R 19467
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#define SPI3_R 19468
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#define USART2_R 19470
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#define USART3_R 19471
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#define UART4_R 19472
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#define UART5_R 19473
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#define UART7_R 19474
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#define UART8_R 19475
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#define I2C1_R 19477
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#define I2C2_R 19478
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#define I2C3_R 19479
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#define I2C5_R 19480
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#define SPDIF_R 19482
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#define CEC_R 19483
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#define DAC12_R 19485
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#define MDIO_R 19847
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#define TIM1_R 19520
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#define TIM8_R 19521
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#define TIM15_R 19522
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#define TIM16_R 19523
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#define TIM17_R 19524
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#define SPI1_R 19528
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#define SPI4_R 19529
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#define SPI5_R 19530
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#define USART6_R 19533
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#define SAI1_R 19536
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#define SAI2_R 19537
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#define SAI3_R 19538
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#define DFSDM_R 19540
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#define FDCAN_R 19544
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#define LPTIM2_R 19584
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#define LPTIM3_R 19585
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#define LPTIM4_R 19586
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#define LPTIM5_R 19587
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#define SAI4_R 19592
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#define SYSCFG_R 19595
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#define VREF_R 19597
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#define TMPSENS_R 19600
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#define PMBCTRL_R 19601
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#define DMA1_R 19648
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#define DMA2_R 19649
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#define DMAMUX_R 19650
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#define ADC12_R 19653
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#define USBO_R 19656
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#define SDMMC3_R 19664
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#define CAMITF_R 19712
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#define CRYP2_R 19716
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#define HASH2_R 19717
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#define RNG2_R 19718
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#define CRC2_R 19719
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#define HSEM_R 19723
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#define MBOX_R 19724
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#define GPIOA_R 19776
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#define GPIOB_R 19777
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#define GPIOC_R 19778
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#define GPIOD_R 19779
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#define GPIOE_R 19780
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#define GPIOF_R 19781
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#define GPIOG_R 19782
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#define GPIOH_R 19783
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#define GPIOI_R 19784
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#define GPIOJ_R 19785
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#define GPIOK_R 19786
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#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
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