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			258 lines
		
	
	
		
			6.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			258 lines
		
	
	
		
			6.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2000
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|  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| 
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| #include <common.h>
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| #include <mpc8xx.h>
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| #include "fpga.h"
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| static long int dram_size (long int, long int *, long int);
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| unsigned long flash_init (void);
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| #define	_NOT_USED_	0xFFFFCC25
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| 
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| const uint sdram_table[] = {
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| 	/*
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| 	 * Single Read. (Offset 00h in UPMA RAM)
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| 	 */
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| 	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Burst Read. (Offset 08h in UPMA RAM)
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| 	 */
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| 	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
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| 	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Single Write. (Offset 18h in UPMA RAM)
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| 	 */
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| 	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Burst Write. (Offset 20h in UPMA RAM)
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| 	 */
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| 	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
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| 	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Refresh. (Offset 30h in UPMA RAM)
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| 	 * (Initialization code at 0x36)
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| 	 */
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| 	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
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| 	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
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| 
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| 	/*
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| 	 * Exception. (Offset 3Ch in UPMA RAM)
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| 	 */
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| 	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
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| };
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| 
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| /*
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|  * Check Board Identity:
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|  */
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| 
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| int checkboard (void)
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| {
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| 	char *s = getenv ("serial#");
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| 
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| 	puts ("Board QUANTUM, Serial No: ");
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| 
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| 	for (; s && *s; ++s) {
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| 		if (*s == ' ')
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| 			break;
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| 		putc (*s);
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| 	}
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| 	putc ('\n');
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| 	return (0);		/* success */
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| }
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| long int initdram (int board_type)
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| {
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| 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
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| 	volatile memctl8xx_t *memctl = &immap->im_memctl;
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| 	long int size9;
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| 
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| 	upmconfig (UPMA, (uint *) sdram_table,
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| 		   sizeof (sdram_table) / sizeof (uint));
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| 
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| 	/* Refresh clock prescalar */
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| 	memctl->memc_mptpr = CFG_MPTPR;
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| 
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| 	memctl->memc_mar = 0x00000088;
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| 
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| 	/* Map controller banks 1 to the SDRAM bank */
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| 	memctl->memc_or1 = CFG_OR1_PRELIM;
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| 	memctl->memc_br1 = CFG_BR1_PRELIM;
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| 
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| 	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
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| 
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| 	udelay (200);
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| 
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| 	/* perform SDRAM initializsation sequence */
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| 
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| 	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
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| 	udelay (1);
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| 
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| 	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
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| 
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| 	udelay (1000);
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| 
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| 	/* Check Bank 0 Memory Size,
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| 	 * 9 column mode
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| 	 */
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| 	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
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| 			   SDRAM_MAX_SIZE);
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| 	/*
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| 	 * Final mapping:
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| 	 */
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| 	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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| 	udelay (1000);
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| 
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| 	return (size9);
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| }
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| /*
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|  * Check memory range for valid RAM. A simple memory test determines
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|  * the actually available RAM size between addresses `base' and
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|  * `base + maxsize'. Some (not all) hardware errors are detected:
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|  * - short between address lines
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|  * - short between data lines
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|  */
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| 
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| static long int dram_size (long int mamr_value, long int *base,
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| 			   long int maxsize)
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| {
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| 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
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| 	volatile memctl8xx_t *memctl = &immap->im_memctl;
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| 	volatile ulong *addr;
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| 	ulong cnt, val, size;
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| 	ulong save[32];		/* to make test non-destructive */
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| 	unsigned char i = 0;
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| 
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| 	memctl->memc_mamr = mamr_value;
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| 
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| 	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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| 		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */
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| 
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| 		save[i++] = *addr;
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| 		*addr = ~cnt;
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| 	}
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| 
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| 	/* write 0 to base address */
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| 	addr = (volatile ulong *)base;
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| 	save[i] = *addr;
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| 	*addr = 0;
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| 
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| 	/* check at base address */
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| 	if ((val = *addr) != 0) {
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| 		/* Restore the original data before leaving the function.
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| 		 */
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| 		*addr = save[i];
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| 		for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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| 			addr = (volatile ulong *) base + cnt;
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| 			*addr = save[--i];
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| 		}
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| 		return (0);
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| 	}
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| 
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| 	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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| 		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */
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| 
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| 		val = *addr;
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| 		*addr = save[--i];
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| 
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| 		if (val != (~cnt)) {
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| 			size = cnt * sizeof (long);
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| 			/* Restore the original data before returning
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| 			 */
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| 			for (cnt <<= 1; cnt <= maxsize / sizeof (long);
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| 			     cnt <<= 1) {
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| 				addr = (volatile ulong *) base + cnt;
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| 				*addr = save[--i];
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| 			}
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| 			return (size);
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| 		}
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| 	}
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| 	return (maxsize);
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| }
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| 
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| /*
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|  * Miscellaneous intialization
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|  */
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| int misc_init_r (void)
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| {
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| 	char *fpga_data_str = getenv ("fpgadata");
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| 	char *fpga_size_str = getenv ("fpgasize");
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| 	void *fpga_data;
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| 	int fpga_size;
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| 	int status;
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| 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
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| 	volatile memctl8xx_t *memctl = &immap->im_memctl;
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| 	int flash_size;
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| 
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| 	/* Remap FLASH according to real size */
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| 	flash_size = flash_init ();
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| 	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
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| 	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
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| 
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| 	if (fpga_data_str && fpga_size_str) {
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| 		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
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| 		fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
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| 
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| 		status = fpga_boot (fpga_data, fpga_size);
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| 		if (status != 0) {
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| 			printf ("\nFPGA: Booting failed ");
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| 			switch (status) {
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| 			case ERROR_FPGA_PRG_INIT_LOW:
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| 				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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| 				break;
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| 			case ERROR_FPGA_PRG_INIT_HIGH:
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| 				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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| 				break;
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| 			case ERROR_FPGA_PRG_DONE:
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| 				printf ("(Timeout: DONE not high after programming FPGA)\n ");
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| 				break;
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| 			}
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| 		}
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| 	}
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| 	return 0;
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| }
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