Shengzhou Liu 0d3972cfcd fsl/ddr: Add workaround for ERRATUM_A009942 ...

During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

2016-01-25 08:24:14 -08:00

..

arm_ddr_gen3.c

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24 13:09:18 -08:00

ctrl_regs.c

driver/ddr/fsl: Update timing config for heavy load

2015-12-13 18:27:27 -08:00

ddr1_dimm_params.c

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2016-01-19 08:31:21 -05:00

ddr2_dimm_params.c

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2016-01-19 08:31:21 -05:00

ddr3_dimm_params.c

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2016-01-19 08:31:21 -05:00

ddr4_dimm_params.c

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23 08:55:53 -07:00

fsl_ddr_gen4.c

fsl/ddr: Add workaround for ERRATUM_A009942

2016-01-25 08:24:14 -08:00

interactive.c

driver/ddr/fsl: Fix driver to support empty first slot

2015-04-23 08:55:53 -07:00

lc_common_dimm_params.c

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2016-01-19 08:31:21 -05:00

main.c

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2016-01-19 08:31:21 -05:00

Makefile

Various Makefiles: Add SPDX-License-Identifier tags

2015-11-10 09:19:52 -05:00

mpc85xx_ddr_gen1.c

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2016-01-19 08:31:21 -05:00

mpc85xx_ddr_gen2.c

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2016-01-19 08:31:21 -05:00

mpc85xx_ddr_gen3.c

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2016-01-19 08:31:21 -05:00

mpc86xx_ddr.c

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2016-01-19 08:31:21 -05:00

options.c

driver/ddr/fsl: Update DDR4 RTT values

2015-12-13 18:27:27 -08:00

util.c

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2016-01-19 08:31:21 -05:00