mirror of
				https://github.com/smaeul/u-boot.git
				synced 2025-11-03 21:48:15 +00:00 
			
		
		
		
	When the ti814x_evm config was removed most, but not all, of the
relevant support code was remove.  Get rid of what was missed.
Fixes: 50b532686849 ("ti814x: Remove platform")
Signed-off-by: Tom Rini <trini@konsulko.com>
		
	
			
		
			
				
	
	
		
			350 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			350 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: GPL-2.0+
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/*
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 * boot-common.c
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 *
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 * Common bootmode functions for omap based boards
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 *
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 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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 */
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#include <common.h>
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#include <ahci.h>
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#include <log.h>
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#include <dm/uclass.h>
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#include <fs_loader.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/omap_common.h>
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#include <asm/omap_sec_common.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <watchdog.h>
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#include <scsi.h>
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#include <i2c.h>
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#include <remoteproc.h>
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#include <image.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IPU1_LOAD_ADDR         (0xa17ff000)
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#define MAX_REMOTECORE_BIN_SIZE (8 * 0x100000)
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#define IPU2_LOAD_ADDR         (IPU1_LOAD_ADDR + MAX_REMOTECORE_BIN_SIZE)
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__weak u32 omap_sys_boot_device(void)
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{
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	return BOOT_DEVICE_NONE;
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}
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void save_omap_boot_params(void)
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{
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	u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
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	struct omap_boot_parameters *omap_boot_params;
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	int sys_boot_device = 0;
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	u32 boot_device;
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	u32 boot_mode;
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	if ((boot_params < NON_SECURE_SRAM_START) ||
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	    (boot_params > NON_SECURE_SRAM_END))
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		return;
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	omap_boot_params = (struct omap_boot_parameters *)boot_params;
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	boot_device = omap_boot_params->boot_device;
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	boot_mode = MMCSD_MODE_UNDEFINED;
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	/* Boot device */
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#ifdef BOOT_DEVICE_NAND_I2C
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	/*
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	 * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
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	 * Otherwise the SPL boot IF can't handle this device correctly.
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	 * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
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	 * Draco leads to this boot-device passed to SPL from the BootROM.
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	 */
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	if (boot_device == BOOT_DEVICE_NAND_I2C)
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		boot_device = BOOT_DEVICE_NAND;
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#endif
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#ifdef BOOT_DEVICE_QSPI_4
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	/*
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	 * We get different values for QSPI_1 and QSPI_4 being used, but
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	 * don't actually care about this difference.  Rather than
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	 * mangle the later code, if we're coming in as QSPI_4 just
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	 * change to the QSPI_1 value.
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	 */
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	if (boot_device == BOOT_DEVICE_QSPI_4)
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		boot_device = BOOT_DEVICE_SPI;
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#endif
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#ifdef CONFIG_TI816X
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	/*
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	 * On PG2.0 and later TI816x the values we get when booting are not the
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	 * same as on PG1.0, which is what the defines are based on.  Update
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	 * them as needed.
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	 */
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	if (get_cpu_rev() != 1) {
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		if (boot_device == 0x05) {
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			omap_boot_params->boot_device = BOOT_DEVICE_NAND;
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			boot_device = BOOT_DEVICE_NAND;
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		}
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		if (boot_device == 0x08) {
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			omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
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			boot_device = BOOT_DEVICE_MMC1;
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		}
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	}
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#endif
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	/*
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	 * When booting from peripheral booting, the boot device is not usable
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	 * as-is (unless there is support for it), so the boot device is instead
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	 * figured out using the SYS_BOOT pins.
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	 */
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	switch (boot_device) {
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#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
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		case BOOT_DEVICE_UART:
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			sys_boot_device = 1;
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			break;
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#endif
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#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
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		case BOOT_DEVICE_USB:
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			sys_boot_device = 1;
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			break;
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#endif
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#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USB_ETHER)
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		case BOOT_DEVICE_USBETH:
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			sys_boot_device = 1;
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			break;
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#endif
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#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH)
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		case BOOT_DEVICE_CPGMAC:
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			sys_boot_device = 1;
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			break;
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#endif
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#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
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		case BOOT_DEVICE_DFU:
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			sys_boot_device = 1;
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			break;
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#endif
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	}
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	if (sys_boot_device) {
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		boot_device = omap_sys_boot_device();
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		/* MMC raw mode will fallback to FS mode. */
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		if ((boot_device >= MMC_BOOT_DEVICES_START) &&
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		    (boot_device <= MMC_BOOT_DEVICES_END))
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			boot_mode = MMCSD_MODE_RAW;
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	}
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	gd->arch.omap_boot_device = boot_device;
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	/* Boot mode */
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#ifdef CONFIG_OMAP34XX
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	if ((boot_device >= MMC_BOOT_DEVICES_START) &&
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	    (boot_device <= MMC_BOOT_DEVICES_END)) {
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		switch (boot_device) {
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		case BOOT_DEVICE_MMC1:
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			boot_mode = MMCSD_MODE_FS;
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			break;
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		case BOOT_DEVICE_MMC2:
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			boot_mode = MMCSD_MODE_RAW;
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			break;
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		}
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	}
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#else
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	/*
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	 * If the boot device was dynamically changed and doesn't match what
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	 * the bootrom initially booted, we cannot use the boot device
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	 * descriptor to figure out the boot mode.
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	 */
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	if ((boot_device == omap_boot_params->boot_device) &&
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	    (boot_device >= MMC_BOOT_DEVICES_START) &&
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	    (boot_device <= MMC_BOOT_DEVICES_END)) {
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		boot_params = omap_boot_params->boot_device_descriptor;
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		if ((boot_params < NON_SECURE_SRAM_START) ||
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		    (boot_params > NON_SECURE_SRAM_END))
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			return;
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		boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
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		if ((boot_params < NON_SECURE_SRAM_START) ||
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		    (boot_params > NON_SECURE_SRAM_END))
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			return;
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		boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
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		if (boot_mode != MMCSD_MODE_FS &&
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		    boot_mode != MMCSD_MODE_RAW)
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#ifdef CONFIG_SUPPORT_EMMC_BOOT
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			boot_mode = MMCSD_MODE_EMMCBOOT;
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#else
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			boot_mode = MMCSD_MODE_UNDEFINED;
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#endif
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	}
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#endif
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	gd->arch.omap_boot_mode = boot_mode;
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#if !defined(CONFIG_TI816X) && \
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    !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
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	/* CH flags */
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	gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
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#endif
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}
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#ifdef CONFIG_SPL_BUILD
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u32 spl_boot_device(void)
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{
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	return gd->arch.omap_boot_device;
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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	return gd->arch.omap_boot_mode;
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}
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int load_firmware(char *name_fw, u32 *loadaddr)
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{
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	struct udevice *fsdev;
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	int size = 0;
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	if (!IS_ENABLED(CONFIG_FS_LOADER))
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		return 0;
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	if (!*loadaddr)
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		return 0;
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	if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
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		size = request_firmware_into_buf(fsdev, name_fw,
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						 (void *)*loadaddr, 0, 0);
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	}
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	return size;
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}
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void spl_boot_ipu(void)
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{
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	int ret, size;
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	u32 loadaddr = IPU1_LOAD_ADDR;
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	if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
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	    !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
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		return;
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	size = load_firmware("dra7-ipu1-fw.xem4", &loadaddr);
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	if (size <= 0) {
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		pr_err("Firmware loading failed\n");
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		goto skip_ipu1;
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	}
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	enable_ipu1_clocks();
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	ret = rproc_dev_init(0);
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	if (ret) {
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		debug("%s: IPU1 failed to initialize on rproc (%d)\n",
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		      __func__, ret);
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		goto skip_ipu1;
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	}
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	ret = rproc_load(0, IPU1_LOAD_ADDR, 0x2000000);
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	if (ret) {
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		debug("%s: IPU1 failed to load on rproc (%d)\n", __func__,
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		      ret);
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		goto skip_ipu1;
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	}
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	debug("Starting IPU1...\n");
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	ret = rproc_start(0);
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	if (ret)
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		debug("%s: IPU1 failed to start (%d)\n", __func__, ret);
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skip_ipu1:
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	loadaddr = IPU2_LOAD_ADDR;
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	size = load_firmware("dra7-ipu2-fw.xem4", &loadaddr);
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	if (size <= 0) {
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		pr_err("Firmware loading failed for ipu2\n");
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		return;
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	}
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	enable_ipu2_clocks();
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	ret = rproc_dev_init(1);
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	if (ret) {
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		debug("%s: IPU2 failed to initialize on rproc (%d)\n", __func__,
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		      ret);
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		return;
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	}
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	ret = rproc_load(1, IPU2_LOAD_ADDR, 0x2000000);
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	if (ret) {
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		debug("%s: IPU2 failed to load on rproc (%d)\n", __func__,
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		      ret);
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		return;
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	}
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	debug("Starting IPU2...\n");
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	ret = rproc_start(1);
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	if (ret)
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		debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
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}
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void spl_board_init(void)
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{
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	/* Prepare console output */
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	preloader_console_init();
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#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
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	gpmc_init();
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#endif
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#if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C)
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	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW)
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	arch_misc_init();
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#endif
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#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
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	hw_watchdog_init();
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#endif
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#ifdef CONFIG_AM33XX
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	am33xx_spl_board_init();
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#endif
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	if (IS_ENABLED(CONFIG_SPL_BUILD) &&
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	    IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
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		spl_boot_ipu();
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}
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
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	image_entry_noargs_t image_entry =
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			(image_entry_noargs_t) spl_image->entry_point;
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	u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
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	debug("image entry point: 0x%lX\n", spl_image->entry_point);
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	/* Pass the saved boot_params from rom code */
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	image_entry((u32 *)boot_params);
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}
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#endif
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#ifdef CONFIG_SCSI_AHCI_PLAT
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void arch_preboot_os(void)
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{
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	ahci_reset((void __iomem *)DWC_AHSATA_BASE);
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}
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#endif
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#ifdef CONFIG_TI_SECURE_DEVICE
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void board_fit_image_post_process(const void *fit, int node, void **p_image,
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				  size_t *p_size)
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{
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	secure_boot_verify_image(p_image, p_size);
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}
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static void tee_image_process(ulong tee_image, size_t tee_size)
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{
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	secure_tee_install((u32)tee_image);
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}
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U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process);
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#endif
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