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smaeul-u-boot/drivers/ddr
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York Sun 0fb7197436 driver/ddr/fsl: Update DDR4 MR6 for Vref range 
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
..
altera
ddr: altera: Repair uninited variable
2015-08-23 11:56:19 +02:00
fsl
driver/ddr/fsl: Update DDR4 MR6 for Vref range
2015-12-13 18:27:27 -08:00
marvell
arm: mvebu: Fix SAR1_CPU_CORE_MASK
2015-11-17 23:41:41 +01:00