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816264fc66
This patch moves mx35 to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) mx35 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx35 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1<<15) /* Software reset */
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#define GPTCR_FRR (1<<9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
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#define GPTCR_TEN (1) /* Timer enable */
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/*
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* nothing really to do with interrupts, just starts up a counter.
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* The 32KHz 32-bit timer overruns in 134217 seconds
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*/
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int timer_init(void)
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{
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int i;
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
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/* setup GP Timer 1 */
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writel(GPTCR_SWR, &gpt->ctrl);
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writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
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for (i = 0; i < 100; i++)
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writel(0, &gpt->ctrl); /* We have no udelay by now */
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writel(0, &gpt->pre); /* prescaler = 1 */
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/* Freerun Mode, 32KHz input */
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writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
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&gpt->ctrl);
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writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
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return 0;
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}
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