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1b8fec1393
APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Stefan Roese <sr@denx.de>
84 lines
3.5 KiB
C
84 lines
3.5 KiB
C
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/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC4xx_ISRAM_H_
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#define _PPC4xx_ISRAM_H_
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/*
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* Internal SRAM
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*/
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_APM821XX)
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#define ISRAM0_DCR_BASE 0x380
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#else
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#define ISRAM0_DCR_BASE 0x020
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#endif
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#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
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#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
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#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
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#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
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#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
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#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
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#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
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#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
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#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
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#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
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#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_APM821XX)
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#define ISRAM1_DCR_BASE 0x0B0
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#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
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#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
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#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
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#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
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#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
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#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
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#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
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#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
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#endif /* CONFIG_460EX || CONFIG_460GT */
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define ISRAM1_SIZE 0x0984 /* OCM size 64k */
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#elif defined(CONFIG_APM821XX)
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#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
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#endif
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/*
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* L2 Cache
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*/
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#if defined (CONFIG_440GX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
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#define L2_CACHE_BASE 0x030
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#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
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#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
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#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
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#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
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#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
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#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
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#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
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#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
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#endif /* CONFIG_440GX */
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#endif /* _PPC4xx_ISRAM_H_ */
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