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96683d3436
Add support for Versal NET mini Quad SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Quad SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
73 lines
1.3 KiB
Plaintext
73 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal NET Mini QSPI Configuration
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*
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* (C) Copyright 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
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*/
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/dts-v1/;
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/ {
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compatible = "xlnx,versal-net-mini";
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Xilinx Versal NET MINI QSPI";
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aliases {
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serial0 = &dcc;
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spi0 = &qspi;
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};
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chosen {
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stdout-path = "serial0:115200";
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};
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memory@bbf00000 {
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device_type = "memory";
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reg = <0 0xbbf00000 0 0x100000>;
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};
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clk150: clk150 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <150000000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "okay";
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bootph-all;
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};
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amba: amba {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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qspi: spi@f1030000 {
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compatible = "xlnx,versal-qspi-1.0";
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status = "okay";
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clock-names = "ref_clk", "pclk";
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num-cs = <1>;
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reg = <0 0xf1030000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk150>, <&clk150>;
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flash0: flash@0 {
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compatible = "n25q512a", "micron,m25p80",
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"jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <20000000>;
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};
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};
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};
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};
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