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0f8106f8e0
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
28 lines
620 B
C
28 lines
620 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#ifndef __STM32_PWR_H_
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#define __STM32_PWR_H_
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/*
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* Offsets of some PWR registers
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*/
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#define PWR_CR1_ODEN BIT(16)
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#define PWR_CR1_ODSWEN BIT(17)
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#define PWR_CSR1_ODRDY BIT(16)
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#define PWR_CSR1_ODSWRDY BIT(17)
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struct stm32_pwr_regs {
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u32 cr1; /* power control register 1 */
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u32 csr1; /* power control/status register 2 */
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};
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#endif /* __STM32_PWR_H_ */
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