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386fca6896
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2024 Altera Corporation <www.altera.com>
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*/
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#ifndef _CLOCK_MANAGER_H_
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#define _CLOCK_MANAGER_H_
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phys_addr_t socfpga_get_clkmgr_addr(void);
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#ifndef __ASSEMBLY__
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void cm_wait_for_lock(u32 mask);
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int cm_wait_for_fsm(void);
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void cm_print_clock_quick_summary(void);
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
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int cm_set_qspi_controller_clk_hz(u32 clk_hz);
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#endif
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/clock_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/clock_manager_arria10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
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#include <asm/arch/clock_manager_s10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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#include <asm/arch/clock_manager_agilex.h>
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#include <asm/arch/clock_manager_agilex5.h>
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#include <asm/arch/clock_manager_n5x.h>
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#endif
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#endif /* _CLOCK_MANAGER_H_ */
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