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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
247 lines
6.9 KiB
C
247 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk.h>
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#include <dm.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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#include <asm/global_data.h>
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#include <linux/io.h>
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#include <linux/bitfield.h>
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#include "mt7621.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const char *const boot_mode[(CHIP_MODE_M >> CHIP_MODE_S) + 1] = {
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[1] = "NAND 2K+64",
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[2] = "SPI-NOR 3-Byte Addr",
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[3] = "SPI-NOR 4-Byte Addr",
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[10] = "NAND 2K+128",
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[11] = "NAND 4K+128",
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[12] = "NAND 4K+256",
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};
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int print_cpuinfo(void)
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{
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void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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u32 val, ver, eco, pkg, core, dram, chipmode;
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u32 cpu_clk, ddr_clk, bus_clk, xtal_clk;
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struct udevice *clkdev;
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const char *bootdev;
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struct clk clk;
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int ret;
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val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
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ver = FIELD_GET(VER_ID_M, val);
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eco = FIELD_GET(ECO_ID_M, val);
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pkg = FIELD_GET(PKG_ID, val);
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core = FIELD_GET(CPU_ID, val);
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val = readl(sysc + SYSCTL_SYSCFG0_REG);
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dram = FIELD_GET(DRAM_TYPE, val);
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chipmode = FIELD_GET(CHIP_MODE_M, val);
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bootdev = boot_mode[chipmode];
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if (!bootdev)
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bootdev = "Unsupported boot mode";
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printf("CPU: MediaTek MT7621%c ver %u, eco %u\n",
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core ? (pkg ? 'A' : 'N') : 'S', ver, eco);
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printf("Boot: DDR%u, %s\n", dram ? 2 : 3, bootdev);
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ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7621_clk),
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&clkdev);
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if (ret)
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return ret;
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clk.dev = clkdev;
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clk.id = MT7621_CLK_CPU;
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cpu_clk = clk_get_rate(&clk);
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clk.id = MT7621_CLK_BUS;
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bus_clk = clk_get_rate(&clk);
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clk.id = MT7621_CLK_DDR;
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ddr_clk = clk_get_rate(&clk);
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clk.id = MT7621_CLK_XTAL;
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xtal_clk = clk_get_rate(&clk);
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/* Set final timer frequency */
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if (cpu_clk)
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gd->arch.timer_freq = cpu_clk / 2;
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printf("Clock: CPU: %uMHz, DDR: %uMT/s, Bus: %uMHz, XTAL: %uMHz\n",
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cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000,
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xtal_clk / 1000000);
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return 0;
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}
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unsigned long get_xtal_mhz(void)
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{
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void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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u32 bs, xtal_sel;
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bs = readl(sysc + SYSCTL_SYSCFG0_REG);
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xtal_sel = FIELD_GET(XTAL_MODE_SEL_M, bs);
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if (xtal_sel <= 2)
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return 20;
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else if (xtal_sel <= 5)
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return 40;
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else
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return 25;
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}
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static void xhci_config_40mhz(void __iomem *usbh)
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{
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writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) |
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FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) |
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FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) |
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FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10,
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usbh + SSUSB_MAC_CK_CTRL_REG);
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writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) |
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FIELD_PREP(SSUSB_PLL_PREDIV_U3_M, 1) |
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FIELD_PREP(SSUSB_PLL_FBKDI_M, 4),
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usbh + DA_SSUSB_U3PHYA_10_REG);
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writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x1e),
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usbh + DA_SSUSB_PLL_FBKDIV_REG);
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writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x1e400000),
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usbh + DA_SSUSB_PLL_PCW_NCPO_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) |
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FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x73),
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usbh + DA_SSUSB_PLL_SSC_DELTA1_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x71) |
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FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a),
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usbh + DA_SSUSB_U3PHYA_21_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x140),
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usbh + SSUSB_U3PHYA_9_REG);
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writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0x11c00000),
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usbh + SSUSB_U3PHYA_3_REG);
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writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) |
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FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1) |
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FIELD_PREP(SSUSB_SYSPLL_PREDIV_M, 1),
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usbh + SSUSB_U3PHYA_1_REG);
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writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0x12) |
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SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN |
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SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN,
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usbh + SSUSB_U3PHYA_2_REG);
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writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) |
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FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) |
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FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1),
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usbh + SSUSB_U3PHYA_11_REG);
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writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) |
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FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) |
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SSUSB_RING_BYPASS_DET,
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usbh + SSUSB_B2_ROSC_0_REG);
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writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) |
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SSUSB_RING_OSC_FRC_SEL,
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usbh + SSUSB_B2_ROSC_1_REG);
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}
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static void xhci_config_25mhz(void __iomem *usbh)
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{
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writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) |
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FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) |
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FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) |
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FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10,
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usbh + SSUSB_MAC_CK_CTRL_REG);
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writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) |
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FIELD_PREP(SSUSB_PLL_FBKDI_M, 4),
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usbh + DA_SSUSB_U3PHYA_10_REG);
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writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) |
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FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x19),
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usbh + DA_SSUSB_PLL_FBKDIV_REG);
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writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x18000000),
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usbh + DA_SSUSB_PLL_PCW_NCPO_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) |
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FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x4a),
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usbh + DA_SSUSB_PLL_SSC_DELTA1_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x48) |
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FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a),
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usbh + DA_SSUSB_U3PHYA_21_REG);
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writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x190),
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usbh + SSUSB_U3PHYA_9_REG);
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writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0xe000000),
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usbh + SSUSB_U3PHYA_3_REG);
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writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) |
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FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1),
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usbh + SSUSB_U3PHYA_1_REG);
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writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0xf) |
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SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN |
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SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN,
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usbh + SSUSB_U3PHYA_2_REG);
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writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) |
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FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) |
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FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1),
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usbh + SSUSB_U3PHYA_11_REG);
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writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) |
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FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) |
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SSUSB_RING_BYPASS_DET,
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usbh + SSUSB_B2_ROSC_0_REG);
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writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) |
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SSUSB_RING_OSC_FRC_SEL,
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usbh + SSUSB_B2_ROSC_1_REG);
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}
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void lowlevel_init(void)
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{
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void __iomem *usbh = ioremap_nocache(SSUSB_BASE, SSUSB_SIZE);
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u32 xtal = get_xtal_mhz();
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/* Setup USB xHCI */
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if (xtal == 40)
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xhci_config_40mhz(usbh);
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else if (xtal == 25)
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xhci_config_25mhz(usbh);
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}
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ulong notrace get_tbclk(void)
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{
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return gd->arch.timer_freq;
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}
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void _machine_restart(void)
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{
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void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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while (1)
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writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
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}
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