mirror of
https://github.com/smaeul/u-boot.git
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313 lines
8.1 KiB
C
313 lines
8.1 KiB
C
/*
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* (C) Copyright 2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#define MEM_MCOPT1_INIT_VAL 0x00800000
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#define MEM_RTR_INIT_VAL 0x04070000
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#define MEM_PMIT_INIT_VAL 0x07c00000
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#define MEM_MB0CF_INIT_VAL 0x00082001
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#define MEM_MB1CF_INIT_VAL 0x04082000
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#define MEM_SDTR1_INIT_VAL 0x00854005
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#define SDRAM0_CFG_ENABLE 0x80000000
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#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */
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int board_early_init_f (void)
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{
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#if 0 /* test-only */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000010);
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mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
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mtdcr (uictr, 0x00000010); /* set int trigger levels */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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#else
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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#endif
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#if 1 /* test-only */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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#endif
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return 0;
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}
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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#if defined(CONFIG_CMD_NAND)
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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#endif
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming G2000");
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} else {
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puts(str);
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}
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putc ('\n');
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return 0;
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}
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/* -------------------------------------------------------------------------
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G2000 rev B is an embeded design. we don't read for spd of this version.
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Doing static SDRAM controller configuration in the following section.
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------------------------------------------------------------------------- */
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long int init_sdram_static_settings(void)
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{
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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/* disable memcontroller so updates work */
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mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
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mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
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mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
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mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
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mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
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mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
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/* SDRAM have a power on delay, 500 micro should do */
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udelay(500);
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mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
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return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */
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}
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long int initdram (int board_type)
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{
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long int ret;
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/* flzt, we can still turn this on in the future */
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/* #ifdef CONFIG_SPD_EEPROM
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ret = spd_sdram ();
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#else
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ret = init_sdram_static_settings();
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#endif
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*/
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ret = init_sdram_static_settings();
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return ret;
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}
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#if 1 /* test-only */
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void sdram_init(void)
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{
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init_sdram_static_settings();
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}
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#endif
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#if 0 /* test-only */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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#endif
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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#if defined(CONFIG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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#if 0 /* test-only !!! */
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int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong ap, cr;
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printf("\nEBC registers for PPC405GP:\n");
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mfebc(pb0ap, ap); mfebc(pb0cr, cr);
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printf("0: AP=%08lx CP=%08lx\n", ap, cr);
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mfebc(pb1ap, ap); mfebc(pb1cr, cr);
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printf("1: AP=%08lx CP=%08lx\n", ap, cr);
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mfebc(pb2ap, ap); mfebc(pb2cr, cr);
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printf("2: AP=%08lx CP=%08lx\n", ap, cr);
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mfebc(pb3ap, ap); mfebc(pb3cr, cr);
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printf("3: AP=%08lx CP=%08lx\n", ap, cr);
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mfebc(pb4ap, ap); mfebc(pb4cr, cr);
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printf("4: AP=%08lx CP=%08lx\n", ap, cr);
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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dumpebc, 1, 1, do_dumpebc,
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"dumpebc - Dump all EBC registers\n",
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NULL
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);
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int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int i;
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printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
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for (i=0; i<=0x1e0; i++) {
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if (!(i % 0x8)) {
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printf("\n%04x ", i);
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}
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printf("%08lx ", get_dcr(i));
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}
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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dumpdcr, 1, 1, do_dumpdcr,
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"dumpdcr - Dump all DCR registers\n",
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NULL
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);
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int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
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printf("\n%04x %08x ", 947, mfspr(947));
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printf("\n%04x %08x ", 9, mfspr(9));
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printf("\n%04x %08x ", 1014, mfspr(1014));
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printf("\n%04x %08x ", 1015, mfspr(1015));
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printf("\n%04x %08x ", 1010, mfspr(1010));
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printf("\n%04x %08x ", 957, mfspr(957));
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printf("\n%04x %08x ", 1008, mfspr(1008));
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printf("\n%04x %08x ", 1018, mfspr(1018));
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printf("\n%04x %08x ", 954, mfspr(954));
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printf("\n%04x %08x ", 950, mfspr(950));
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printf("\n%04x %08x ", 951, mfspr(951));
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printf("\n%04x %08x ", 981, mfspr(981));
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printf("\n%04x %08x ", 980, mfspr(980));
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printf("\n%04x %08x ", 982, mfspr(982));
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printf("\n%04x %08x ", 1012, mfspr(1012));
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printf("\n%04x %08x ", 1013, mfspr(1013));
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printf("\n%04x %08x ", 948, mfspr(948));
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printf("\n%04x %08x ", 949, mfspr(949));
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printf("\n%04x %08x ", 1019, mfspr(1019));
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printf("\n%04x %08x ", 979, mfspr(979));
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printf("\n%04x %08x ", 8, mfspr(8));
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printf("\n%04x %08x ", 945, mfspr(945));
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printf("\n%04x %08x ", 987, mfspr(987));
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printf("\n%04x %08x ", 287, mfspr(287));
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printf("\n%04x %08x ", 953, mfspr(953));
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printf("\n%04x %08x ", 955, mfspr(955));
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printf("\n%04x %08x ", 272, mfspr(272));
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printf("\n%04x %08x ", 273, mfspr(273));
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printf("\n%04x %08x ", 274, mfspr(274));
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printf("\n%04x %08x ", 275, mfspr(275));
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printf("\n%04x %08x ", 260, mfspr(260));
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printf("\n%04x %08x ", 276, mfspr(276));
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printf("\n%04x %08x ", 261, mfspr(261));
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printf("\n%04x %08x ", 277, mfspr(277));
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printf("\n%04x %08x ", 262, mfspr(262));
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printf("\n%04x %08x ", 278, mfspr(278));
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printf("\n%04x %08x ", 263, mfspr(263));
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printf("\n%04x %08x ", 279, mfspr(279));
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printf("\n%04x %08x ", 26, mfspr(26));
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printf("\n%04x %08x ", 27, mfspr(27));
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printf("\n%04x %08x ", 990, mfspr(990));
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printf("\n%04x %08x ", 991, mfspr(991));
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printf("\n%04x %08x ", 956, mfspr(956));
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printf("\n%04x %08x ", 284, mfspr(284));
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printf("\n%04x %08x ", 285, mfspr(285));
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printf("\n%04x %08x ", 986, mfspr(986));
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printf("\n%04x %08x ", 984, mfspr(984));
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printf("\n%04x %08x ", 256, mfspr(256));
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printf("\n%04x %08x ", 1, mfspr(1));
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printf("\n%04x %08x ", 944, mfspr(944));
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printf("\n");
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return 0;
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}
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U_BOOT_CMD(
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dumpspr, 1, 1, do_dumpspr,
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"dumpspr - Dump all SPR registers\n",
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NULL
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);
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#endif
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