mirror of
https://github.com/smaeul/u-boot.git
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
506 lines
13 KiB
ArmAsm
506 lines
13 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for MPL VCMA9 by
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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* (C) Copyright 2002, 2003, 2004, 2005
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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/* register definitions */
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#define PLD_BASE 0x28000000
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#define MISC_REG 0x103
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#define SDRAM_REG 0x106
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#define BWSCON 0x48000000
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#define CLKBASE 0x4C000000
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#define LOCKTIME 0x0
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#define MPLLCON 0x4
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#define UPLLCON 0x8
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#define GPIOBASE 0x56000000
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#define GSTATUS1 0xB0
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#define FASTCPU 0x02
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/* some parameters for the board */
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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#define DW32 (0x2)
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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/* BANKSIZE */
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#define BURST_EN (0x1<<7)
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/* BANK0CON 200 */
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#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
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#define B0_Tcoh_200 0x0 /* 0clk */
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#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
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#define B0_Tacp_200 0x0 /* page mode is not used */
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#define B0_PMC_200 0x0 /* page mode disabled */
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/* BANK0CON 250 */
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#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
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#define B0_Tcoh_250 0x0 /* 0clk */
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#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
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#define B0_Tacp_250 0x0 /* page mode is not used */
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#define B0_PMC_250 0x0 /* page mode disabled */
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/* BANK0CON 266 */
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#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
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#define B0_Tcoh_266 0x0 /* 0clk */
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#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
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#define B0_Tacp_266 0x0 /* page mode is not used */
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#define B0_PMC_266 0x0 /* page mode disabled */
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/* BANK1CON 200 */
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#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
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#define B1_Tcoh_200 0x0 /* 0clk */
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#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_200 0x0 /* page mode is not used */
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#define B1_PMC_200 0x0 /* page mode disabled */
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/* BANK1CON 250 */
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#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
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#define B1_Tcoh_250 0x0 /* 0clk */
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#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_250 0x0 /* page mode is not used */
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#define B1_PMC_250 0x0 /* page mode disabled */
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/* BANK1CON 266 */
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#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
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#define B1_Tcoh_266 0x0 /* 0clk */
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#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_266 0x0 /* page mode is not used */
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#define B1_PMC_266 0x0 /* page mode disabled */
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/* BANK2CON 200 + 250 + 266 */
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#define B2_Tacs 0x3 /* 4clk */
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#define B2_Tcos 0x3 /* 4clk */
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#define B2_Tacc 0x7 /* 14clk */
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#define B2_Tcoh 0x3 /* 4clk */
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#define B2_Tcah 0x3 /* 4clk */
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#define B2_Tacp 0x0 /* page mode is not used */
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#define B2_PMC 0x0 /* page mode disabled */
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/* BANK3CON 200 + 250 + 266 */
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#define B3_Tacs 0x3 /* 4clk */
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#define B3_Tcos 0x3 /* 4clk */
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#define B3_Tacc 0x7 /* 14clk */
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#define B3_Tcoh 0x3 /* 4clk */
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#define B3_Tcah 0x3 /* 4clk */
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#define B3_Tacp 0x0 /* page mode is not used */
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#define B3_PMC 0x0 /* page mode disabled */
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/* BANK4CON 200 */
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#define B4_Tacs_200 0x1 /* 1clk */
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#define B4_Tcos_200 0x3 /* 4clk */
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#define B4_Tacc_200 0x7 /* 14clk */
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#define B4_Tcoh_200 0x3 /* 4clk */
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#define B4_Tcah_200 0x2 /* 2clk */
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#define B4_Tacp_200 0x0 /* page mode is not used */
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#define B4_PMC_200 0x0 /* page mode disabled */
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/* BANK4CON 250 */
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#define B4_Tacs_250 0x1 /* 1clk */
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#define B4_Tcos_250 0x3 /* 4clk */
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#define B4_Tacc_250 0x7 /* 14clk */
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#define B4_Tcoh_250 0x3 /* 4clk */
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#define B4_Tcah_250 0x2 /* 2clk */
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#define B4_Tacp_250 0x0 /* page mode is not used */
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#define B4_PMC_250 0x0 /* page mode disabled */
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/* BANK4CON 266 */
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#define B4_Tacs_266 0x1 /* 1clk */
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#define B4_Tcos_266 0x3 /* 4clk */
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#define B4_Tacc_266 0x7 /* 14clk */
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#define B4_Tcoh_266 0x3 /* 4clk */
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#define B4_Tcah_266 0x2 /* 2clk */
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#define B4_Tacp_266 0x0 /* page mode is not used */
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#define B4_PMC_266 0x0 /* page mode disabled */
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/* BANK5CON 200 */
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#define B5_Tacs_200 0x0 /* 0clk */
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#define B5_Tcos_200 0x3 /* 4clk */
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#define B5_Tacc_200 0x4 /* 6clk */
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#define B5_Tcoh_200 0x3 /* 4clk */
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#define B5_Tcah_200 0x1 /* 1clk */
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#define B5_Tacp_200 0x0 /* page mode is not used */
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#define B5_PMC_200 0x0 /* page mode disabled */
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/* BANK5CON 250 */
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#define B5_Tacs_250 0x0 /* 0clk */
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#define B5_Tcos_250 0x3 /* 4clk */
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#define B5_Tacc_250 0x5 /* 8clk */
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#define B5_Tcoh_250 0x3 /* 4clk */
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#define B5_Tcah_250 0x1 /* 1clk */
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#define B5_Tacp_250 0x0 /* page mode is not used */
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#define B5_PMC_250 0x0 /* page mode disabled */
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/* BANK5CON 266 */
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#define B5_Tacs_266 0x0 /* 0clk */
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#define B5_Tcos_266 0x3 /* 4clk */
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#define B5_Tacc_266 0x5 /* 8clk */
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#define B5_Tcoh_266 0x3 /* 4clk */
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#define B5_Tcah_266 0x1 /* 1clk */
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#define B5_Tacp_266 0x0 /* page mode is not used */
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#define B5_PMC_266 0x0 /* page mode disabled */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd_200 0x0 /* 2clk */
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#define B6_Trcd_250 0x1 /* 3clk */
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#define B6_Trcd_266 0x1 /* 3clk */
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#define B6_SCAN 0x2 /* 10bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd_200 0x0 /* 2clk */
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#define B7_Trcd_250 0x1 /* 3clk */
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#define B7_Trcd_266 0x1 /* 3clk */
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#define B7_SCAN 0x2 /* 10bit */
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/* REFRESH parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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#define Trp_200 0x0 /* 2clk */
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#define Trp_250 0x1 /* 3clk */
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#define Trp_266 0x1 /* 3clk */
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#define Tsrc_200 0x1 /* 5clk */
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#define Tsrc_250 0x2 /* 6clk */
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#define Tsrc_266 0x3 /* 7clk */
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/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
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#define REFCNT_200 489
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/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
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#define REFCNT_250 99
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/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
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#define REFCNT_266 0
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/**************************************/
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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/* use r0 to relocate DATA read/write to flash rather than memory ! */
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ldr r0, _TEXT_BASE
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ldr r13, =BWSCON
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/* enable minimal access to PLD */
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ldr r1, [r13] /* load default BWSCON */
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orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
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str r1, [r13] /* set BWSCON */
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ldr r1, =0x7FF0 /* select slowest timing */
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str r1, [r13, #0x18] /* set BANKCON5 */
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ldr r1, =PLD_BASE
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ldr r2, =SETUPDATA
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ldrb r1, [r1, #MISC_REG]
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sub r2, r2, r0
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tst r1, #FASTCPU /* FASTCPU available ? */
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addeq r2, r2, #SETUPENTRY_SIZE
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/* memory control configuration */
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/* r2 = pointer into timing table */
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/* r13 = pointer to MEM controller regs (starting with BWSCON) */
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add r3, r2, #CSDATA_OFFSET
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add r4, r3, #CSDATAENTRY_SIZE
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0:
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ldr r1, [r3], #4
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str r1, [r13], #4
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cmp r3, r4
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bne 0b
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/* PLD access is now possible */
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/* r3 = SDRAMDATA
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/* r13 = pointer to MEM controller regs */
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ldr r1, =PLD_BASE
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mov r4, #SDRAMENTRY_SIZE
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ldrb r1, [r1, #SDRAM_REG]
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/* calculate start and end point */
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mla r3, r4, r1, r3
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add r4, r3, r4
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0:
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ldr r1, [r3], #4
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str r1, [r13], #4
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cmp r3, r4
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bne 0b
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/* setup MPLL registers */
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ldr r1, =CLKBASE
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ldr r4, =0xFFFFFF
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add r3, r2, #4 /* r3 points to PLL values */
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str r4, [r1, #LOCKTIME]
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ldmia r3, {r4,r5}
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str r5, [r1, #UPLLCON] /* writing PLL register */
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/* !! order seems to be important !! */
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/* a little delay */
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ldr r3, =0x4000
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0:
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subs r3, r3, #1
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bne 0b
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str r4, [r1, #MPLLCON] /* writing PLL register */
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/* !! order seems to be important !! */
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/* a little delay */
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ldr r3, =0x4000
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0:
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subs r3, r3, #1
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
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((bws1) << 4) + \
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((bws2) << 8) + \
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((bws3) << 12) + \
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((bws4) << 16) + \
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((bws5) << 20) + \
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((bws6) << 24) + \
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((bws7) << 28)
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#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
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((tacs) << 13) + \
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((tcos) << 11) + \
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((tacc) << 8) + \
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((tcoh) << 6) + \
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((tcah) << 4) + \
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((tacp) << 2) + \
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(pmc)
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#define MK_BANKCON_SDRAM(trcd, scan) \
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((0x03) << 15) + \
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((trcd) << 2) + \
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(scan)
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#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
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((enable) << 23) + \
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((trefmd) << 22) + \
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((trp) << 20) + \
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((tsrc) << 18) + \
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(cnt)
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SETUPDATA:
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.word 0x32410002
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/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
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.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
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/* PLL values for USB clock */
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.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
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/* timing for 250 MHz*/
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0:
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.equiv CSDATA_OFFSET, (. - SETUPDATA)
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.word MK_BWSCON(DW16, \
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DW32, \
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DW32, \
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DW16 + WAIT + UBLB, \
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DW8 + UBLB, \
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DW32, \
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DW32)
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.word MK_BANKCON(B0_Tacs_250, \
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B0_Tcos_250, \
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B0_Tacc_250, \
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B0_Tcoh_250, \
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B0_Tcah_250, \
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B0_Tacp_250, \
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B0_PMC_250)
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.word MK_BANKCON(B1_Tacs_250, \
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B1_Tcos_250, \
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B1_Tacc_250, \
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B1_Tcoh_250, \
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B1_Tcah_250, \
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B1_Tacp_250, \
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B1_PMC_250)
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.word MK_BANKCON(B2_Tacs, \
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B2_Tcos, \
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B2_Tacc, \
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B2_Tcoh, \
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B2_Tcah, \
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B2_Tacp, \
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B2_PMC)
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.word MK_BANKCON(B3_Tacs, \
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B3_Tcos, \
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B3_Tacc, \
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B3_Tcoh, \
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B3_Tcah, \
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B3_Tacp, \
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B3_PMC)
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.word MK_BANKCON(B4_Tacs_250, \
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B4_Tcos_250, \
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B4_Tacc_250, \
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B4_Tcoh_250, \
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B4_Tcah_250, \
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B4_Tacp_250, \
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B4_PMC_250)
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.word MK_BANKCON(B5_Tacs_250, \
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B5_Tcos_250, \
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B5_Tacc_250, \
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B5_Tcoh_250, \
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B5_Tcah_250, \
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B5_Tacp_250, \
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B5_PMC_250)
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.equiv CSDATAENTRY_SIZE, (. - 0b)
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/* 4Mx8x4 */
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0:
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.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
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.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
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.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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.equiv SDRAMENTRY_SIZE, (. - 0b)
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/* 8Mx8x4 */
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.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
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.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
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.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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/* 2Mx8x4 */
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.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
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.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
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.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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/* 4Mx8x2 */
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.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
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.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
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.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
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.word 0x32410000
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/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
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.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
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/* PLL values for USB clock */
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.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
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/* timing for 200 MHz and default*/
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.word MK_BWSCON(DW16, \
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DW32, \
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DW32, \
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DW16 + WAIT + UBLB, \
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DW8 + UBLB, \
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DW32, \
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DW32)
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.word MK_BANKCON(B0_Tacs_200, \
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B0_Tcos_200, \
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B0_Tacc_200, \
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B0_Tcoh_200, \
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B0_Tcah_200, \
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B0_Tacp_200, \
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B0_PMC_200)
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|
|
|
.word MK_BANKCON(B1_Tacs_200, \
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B1_Tcos_200, \
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|
B1_Tacc_200, \
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B1_Tcoh_200, \
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B1_Tcah_200, \
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|
B1_Tacp_200, \
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B1_PMC_200)
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|
|
|
.word MK_BANKCON(B2_Tacs, \
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|
B2_Tcos, \
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|
B2_Tacc, \
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|
B2_Tcoh, \
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|
B2_Tcah, \
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|
B2_Tacp, \
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|
B2_PMC)
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|
|
|
.word MK_BANKCON(B3_Tacs, \
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|
B3_Tcos, \
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|
B3_Tacc, \
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|
B3_Tcoh, \
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|
B3_Tcah, \
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|
B3_Tacp, \
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|
B3_PMC)
|
|
|
|
.word MK_BANKCON(B4_Tacs_200, \
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|
B4_Tcos_200, \
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|
B4_Tacc_200, \
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|
B4_Tcoh_200, \
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|
B4_Tcah_200, \
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|
B4_Tacp_200, \
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|
B4_PMC_200)
|
|
|
|
.word MK_BANKCON(B5_Tacs_200, \
|
|
B5_Tcos_200, \
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|
B5_Tacc_200, \
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|
B5_Tcoh_200, \
|
|
B5_Tcah_200, \
|
|
B5_Tacp_200, \
|
|
B5_PMC_200)
|
|
|
|
/* 4Mx8x4 */
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|
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
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|
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
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|
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
|
.word 0x32 + BURST_EN
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|
.word 0x30
|
|
.word 0x30
|
|
|
|
/* 8Mx8x4 */
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|
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
|
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
|
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
|
.word 0x32 + BURST_EN
|
|
.word 0x30
|
|
.word 0x30
|
|
|
|
/* 2Mx8x4 */
|
|
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
|
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
|
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
|
.word 0x32 + BURST_EN
|
|
.word 0x30
|
|
.word 0x30
|
|
|
|
/* 4Mx8x2 */
|
|
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
|
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
|
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
|
.word 0x32 + BURST_EN
|
|
.word 0x30
|
|
.word 0x30
|
|
|
|
.equiv SETUPDATA_SIZE, (. - SETUPDATA)
|