mirror of
https://github.com/smaeul/u-boot.git
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266 lines
5.0 KiB
ArmAsm
266 lines
5.0 KiB
ArmAsm
/*
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* Cache setting */
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mov.l CCR1_A ,r1
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mov.l CCR1_D ,r0
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mov.l r0,@r1
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/* ConfigurePortPins */
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mov.l PECRL3_A, r1
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mov.l PECRL3_D, r0
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mov.w r0,@r1
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mov.l PCCRL4_A, r1
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mov.l PCCRL4_D0, r0
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mov.w r0,@r1
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mov.l PECRL4_A, r1
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mov.l PECRL4_D0, r0
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mov.w r0,@r1
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mov.l PEIORL_A, r1
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mov.l PEIORL_D0, r0
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mov.w r0,@r1
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mov.l PCIORL_A, r1
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mov.l PCIORL_D, r0
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mov.w r0,@r1
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mov.l PFCRH2_A, r1
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mov.l PFCRH2_D, r0
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mov.w r0,@r1
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mov.l PFCRH3_A, r1
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mov.l PFCRH3_D, r0
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mov.w r0,@r1
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mov.l PFCRH1_A, r1
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mov.l PFCRH1_D, r0
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mov.w r0,@r1
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mov.l PFIORH_A, r1
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mov.l PFIORH_D, r0
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mov.w r0,@r1
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mov.l PECRL1_A, r1
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mov.l PECRL1_D0, r0
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mov.w r0,@r1
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mov.l PEIORL_A, r1
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mov.l PEIORL_D1, r0
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mov.w r0,@r1
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/* Configure Operating Frequency */
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mov.l WTCSR_A ,r1
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mov.l WTCSR_D0 ,r0
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mov.w r0,@r1
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mov.l WTCSR_A ,r1
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mov.l WTCSR_D1 ,r0
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mov.w r0,@r1
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mov.l WTCNT_A ,r1
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mov.l WTCNT_D ,r0
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mov.w r0,@r1
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/* Set clock mode*/
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mov.l FRQCR_A,r1
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mov.l FRQCR_D,r0
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mov.w r0,@r1
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/* Configure Bus And Memory */
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init_bsc_cs0:
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mov.l PCCRL4_A,r1
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mov.l PCCRL4_D1,r0
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mov.w r0,@r1
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mov.l PECRL1_A,r1
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mov.l PECRL1_D1,r0
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mov.w r0,@r1
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mov.l CMNCR_A,r1
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mov.l CMNCR_D,r0
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mov.l r0,@r1
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mov.l SC0BCR_A,r1
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mov.l SC0BCR_D,r0
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mov.l r0,@r1
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mov.l CS0WCR_A,r1
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mov.l CS0WCR_D,r0
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mov.l r0,@r1
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init_bsc_cs1:
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mov.l PECRL4_A,r1
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mov.l PECRL4_D1,r0
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mov.w r0,@r1
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mov.l CS1WCR_A,r1
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mov.l CS1WCR_D,r0
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mov.l r0,@r1
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init_sdram:
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mov.l PCCRL2_A,r1
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mov.l PCCRL2_D,r0
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mov.w r0,@r1
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mov.l PCCRL4_A,r1
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mov.l PCCRL4_D2,r0
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mov.w r0,@r1
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mov.l PCCRL1_A,r1
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mov.l PCCRL1_D,r0
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mov.w r0,@r1
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mov.l PCCRL3_A,r1
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mov.l PCCRL3_D,r0
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mov.w r0,@r1
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mov.l CS3BCR_A,r1
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mov.l CS3BCR_D,r0
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mov.l r0,@r1
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mov.l CS3WCR_A,r1
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mov.l CS3WCR_D,r0
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mov.l r0,@r1
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mov.l SDCR_A,r1
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mov.l SDCR_D,r0
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mov.l r0,@r1
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mov.l RTCOR_A,r1
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mov.l RTCOR_D,r0
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mov.l r0,@r1
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mov.l RTCSR_A,r1
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mov.l RTCSR_D,r0
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mov.l r0,@r1
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/* wait 200us */
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mov.l REPEAT_D,r3
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mov #0,r2
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repeat0:
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add #1,r2
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cmp/hs r3,r2
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bf repeat0
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nop
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mov.l SDRAM_MODE, r1
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mov #0,r0
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mov.l r0, @r1
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nop
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rts
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.align 4
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CCR1_A: .long CCR1
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CCR1_D: .long 0x0000090B
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PCCRL4_A: .long 0xFFFE3910
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PCCRL4_D0: .long 0x00000000
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PECRL4_A: .long 0xFFFE3A10
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PECRL4_D0: .long 0x00000000
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PECRL3_A: .long 0xFFFE3A12
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PECRL3_D: .long 0x00000000
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PEIORL_A: .long 0xFFFE3A06
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PEIORL_D0: .long 0x00001C00
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PEIORL_D1: .long 0x00001C02
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PCIORL_A: .long 0xFFFE3906
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PCIORL_D: .long 0x00004000
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PFCRH2_A: .long 0xFFFE3A8C
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PFCRH2_D: .long 0x00000000
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PFCRH3_A: .long 0xFFFE3A8A
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PFCRH3_D: .long 0x00000000
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PFCRH1_A: .long 0xFFFE3A8E
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PFCRH1_D: .long 0x00000000
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PFIORH_A: .long 0xFFFE3A84
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PFIORH_D: .long 0x00000729
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PECRL1_A: .long 0xFFFE3A16
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PECRL1_D0: .long 0x00000033
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WTCSR_A: .long 0xFFFE0000
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WTCSR_D0: .long 0x0000A518
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WTCSR_D1: .long 0x0000A51D
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WTCNT_A: .long 0xFFFE0002
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WTCNT_D: .long 0x00005A84
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FRQCR_A: .long 0xFFFE0010
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FRQCR_D: .long 0x00000104
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PCCRL4_D1: .long 0x00000010
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PECRL1_D1: .long 0x00000133
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CMNCR_A: .long 0xFFFC0000
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CMNCR_D: .long 0x00001810
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SC0BCR_A: .long 0xFFFC0004
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SC0BCR_D: .long 0x10000400
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CS0WCR_A: .long 0xFFFC0028
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CS0WCR_D: .long 0x00000B41
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PECRL4_D1: .long 0x00000100
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CS1WCR_A: .long 0xFFFC002C
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CS1WCR_D: .long 0x00000B01
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PCCRL4_D2: .long 0x00000011
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PCCRL3_A: .long 0xFFFE3912
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PCCRL3_D: .long 0x00000011
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PCCRL2_A: .long 0xFFFE3914
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PCCRL2_D: .long 0x00001111
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PCCRL1_A: .long 0xFFFE3916
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PCCRL1_D: .long 0x00001010
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PDCRL4_A: .long 0xFFFE3990
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PDCRL4_D: .long 0x00000011
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PDCRL3_A: .long 0xFFFE3992
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PDCRL3_D: .long 0x00000011
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PDCRL2_A: .long 0xFFFE3994
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PDCRL2_D: .long 0x00001111
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PDCRL1_A: .long 0xFFFE3996
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PDCRL1_D: .long 0x00001000
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CS3BCR_A: .long 0xFFFC0010
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CS3BCR_D: .long 0x00004400
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CS3WCR_A: .long 0xFFFC0034
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CS3WCR_D: .long 0x00002892
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SDCR_A: .long 0xFFFC004C
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SDCR_D: .long 0x00000809
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RTCOR_A: .long 0xFFFC0058
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RTCOR_D: .long 0xA55A0041
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RTCSR_A: .long 0xFFFC0050
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RTCSR_D: .long 0xa55a0010
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STBCR3_A: .long 0xFFFE0408
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STBCR3_D: .long 0x00000000
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STBCR4_A: .long 0xFFFE040C
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STBCR4_D: .long 0x00000008
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STBCR5_A: .long 0xFFFE0410
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STBCR5_D: .long 0x00000000
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STBCR6_A: .long 0xFFFE0414
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STBCR6_D: .long 0x00000002
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SDRAM_MODE: .long 0xFFFC5040
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REPEAT_D: .long 0x00009C40
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