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2c2cc3e9c0
The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
29 lines
491 B
C
29 lines
491 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm common pin control data.
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*
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* Copyright (C) 2023 Linaro Ltd.
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*/
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#ifndef _QCOM_GPIO_H_
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#define _QCOM_GPIO_H_
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#include <asm/types.h>
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#include <stdbool.h>
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struct msm_pin_data {
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int pin_count;
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const unsigned int *pin_offsets;
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};
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static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
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{
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u32 out = (selector * 0x1000);
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if (offs)
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return out + offs[selector];
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return out;
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}
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#endif /* _QCOM_GPIO_H_ */
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