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664b652058
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
37 lines
668 B
C
37 lines
668 B
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __FSL_CSU_H__
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#define __FSL_CSU_H__
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enum csu_cslx_access {
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CSU_NS_SUP_R = 0x08,
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CSU_NS_SUP_W = 0x80,
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CSU_NS_SUP_RW = 0x88,
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CSU_NS_USER_R = 0x04,
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CSU_NS_USER_W = 0x40,
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CSU_NS_USER_RW = 0x44,
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CSU_S_SUP_R = 0x02,
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CSU_S_SUP_W = 0x20,
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CSU_S_SUP_RW = 0x22,
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CSU_S_USER_R = 0x01,
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CSU_S_USER_W = 0x10,
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CSU_S_USER_RW = 0x11,
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CSU_ALL_RW = 0xff,
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};
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struct csu_ns_dev {
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unsigned long ind;
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uint32_t val;
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};
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void enable_layerscape_ns_access(void);
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void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
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void set_pcie_ns_access(int pcie, u16 val);
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#endif
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